Javier J. Sieiro

12 papers Journal 8Unranked 4
YearRankTypeTitle / Venue / Authors
2020 J jnl
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fábio Passos, Elisenda Roca, Javier J. Sieiro, Rafaella Fiorelli, Rafael Castro-López, José María López-Villegas, Francisco V. Fernández
2020 J jnl
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology.
IEEE Access
Fábio Passos, Elisenda Roca, Ricardo Martins, Nuno Lourenço, Saiyd Ahyoune, Javier J. Sieiro, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2019 J jnl
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta
2018 — conf
Fabrication of Full-3D Printed Electronics RF Passive Components and Circuits.
PRIME
Arnau Salas Barenys, Neus Vidal, Javier J. Sieiro, José María López-Villegas, B. Medina-Rodriguez, F. M. Ramos
2018 J jnl
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator.
Integr.
Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández
2017 J jnl
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Javier J. Sieiro, José María López-Villegas, Neus Vidal
2017 — conf
Extending the frequency range of quasi-static electromagnetic solvers.
SMACD
Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández
2016 J jnl
Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques.
Integr.
Elisenda Roca, Javier J. Sieiro
2014 J jnl
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier J. Sieiro, Neus Vidal, José María López-Villegas
2012 — conf
Compact class-AB follower for wideband closed loop line drivers.
ICECS
David Gascon, Andreu Sanuy, Javier J. Sieiro
2010 J jnl
Low-power current-reused RF front-end based on optimized transformers topology.
Integr.
Ignacio Gil, Ignasi Cairó, Javier J. Sieiro, José María López-Villegas
2010 — conf
Optimized passive devices for low-power LNA design.
ICECS
Ignacio Gil, Raúl Fernández, Javier J. Sieiro, José María López-Villegas