Javier Hormigo

59 papers A 2B 3C 9Misc 1Journal 26Unranked 18

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Advanced Quantization Schemes to Increase Accuracy, Reduce Area, and Lower Power Consumption in FFT Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Mario Garrido, Víctor Manuel Bautista, Alejandro Portas, Javier Hormigo
2025	—	`conf`	Configurable Ultra-High-Throughput QRD FPGA Accelerators for Small Matrices. DCIS Pablo Hormigo-Jiménez, Javier Hormigo
2025	J	`jnl`	Leveraging SYCL for Heterogeneous cDTW Computation on CPU, GPU, and FPGA. Concurr. Comput. Pract. Exp. Cristian Campos, Rafael Asenjo, Javier Hormigo, Angeles G. Navarro
2024	—	`conf`	Computing DTWs on CPU, GPU and FPGA with SYCL. Euro-Par Workshops (1) Cristian Campos, Rafael Asenjo, Javier Hormigo, Angeles G. Navarro
2024	J	`jnl`	HUB Meets Posit: Arithmetic Units Implementation. IEEE Trans. Circuits Syst. II Express Briefs Raul Murillo, Javier Hormigo, Alberto A. Del Barrio, Guillermo Botella
2023	—	`conf`	High-Throughput DTW accelerator with minimum area in AMD FPGA by HLS. DCIS Marco Hormigo-Jiménez, Javier Hormigo
2022	J	`jnl`	High-Radix Formats for Enhancing Floating-Point FPGA Implementations. Circuits Syst. Signal Process. Julio Villalba, Javier Hormigo
2021	J	`jnl`	Efficient Floating-Point Givens Rotation Unit. Circuits Syst. Signal Process. Javier Hormigo, Sergio D. Muñoz
2021	C	`conf`	FPGA acceleration of bit-true simulations for word-length optimization. ARITH Javier Hormigo, Gabriel Caffarena
2020	J	`jnl`	Efficient Floating-Point Givens Rotation Unit. CoRR Javier Hormigo, Sergio D. Muñoz
2020	C	`conf`	Floating-Point Fused Multiply-Add under HUB Format. ARITH Javier Hormigo, Julio Villalba-Moreno, Sonia Gonzalez-Navarro
2020	J	`jnl`	New Results on Non-Normalized Floating-Point Formats. IEEE Trans. Computers Sonia González-Navarro, Javier Hormigo
2019	J	`jnl`	Designing a Project for Learning Industry 4.0 by Applying IoT to Urban Garden. Rev. Iberoam. de Tecnol. del Aprendiz. Javier Hormigo, Andrés Rodríguez
2019	J	`jnl`	Fast HUB Floating-Point Adder for FPGA. IEEE Trans. Circuits Syst. II Express Briefs Julio Villalba, Javier Hormigo, Sonia González-Navarro
2019	C	`conf`	Reproducible Summation Under HUB Format. ARITH Julio Villalba-Moreno, Javier Hormigo, Francisco J. Jaime
2018	J	`jnl`	Unbiased Rounding for HUB Floating-Point Addition. IEEE Trans. Computers Julio Villalba-Moreno, Javier Hormigo, Sonia González-Navarro
2017	C	`conf`	Floating Point Square Root under HUB Format. ICCD Julio Villalba-Moreno, Javier Hormigo
2017	J	`jnl`	HUB Floating Point for Improving FPGA Implementations of DSP Applications. IEEE Trans. Circuits Syst. II Express Briefs Javier Hormigo, Julio Villalba
2017	J	`jnl`	Introduction to the Special Issue on Computer Arithmetic. IEEE Trans. Computers Javier Hormigo, Jean-Michel Muller, Stuart F. Oberman, Nathalie Revol, Arnaud Tisserand, Julio Villalba-Moreno
2017	C	`conf`	Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems. ARITH Sonia González-Navarro, Javier Hormigo
2016	C	`ed.`	23nd IEEE Symposium on Computer Arithmetic, ARITH 2016, Silicon Valley, CA, USA, July 10-13, 2016 ARITH Paolo Montuschi, Michael J. Schulte, Javier Hormigo, Stuart F. Oberman, Nathalie Revol
2016	J	`jnl`	Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest. IEEE Trans. Very Large Scale Integr. Syst. Javier Hormigo, Julio Villalba
2016	J	`jnl`	New Formats for Computing with Real-Numbers under Round-to-Nearest. IEEE Trans. Computers Javier Hormigo, Julio Villalba
2015	J	`jnl`	High-Throughput FPGA Implementation of QR Decomposition. IEEE Trans. Circuits Syst. II Express Briefs Sergio D. Muñoz, Javier Hormigo
2015	—	`conf`	Improving fixed-point implementation of QR decomposition by rounding-to-nearest. ISCE Sergio D. Muñoz, Javier Hormigo
2015	—	`conf`	Simplified floating-point units for high dynamic range image and video systems. ISCE Javier Hormigo, Julio Villalba
2014	Misc	`conf`	Optimizing DSP circuits by a new family of arithmetic operators. ACSSC Javier Hormigo, Julio Villalba
2013	C	`conf`	Efficient floating-point representation for balanced codes for FPGA devices. ICCD Julio Villalba, Javier Hormigo, Francisco Corbera, Mario A. González, Emilio L. Zapata
2013	J	`jnl`	Multioperand Redundant Adders on FPGAs. IEEE Trans. Computers Javier Hormigo, Julio Villalba, Emilio L. Zapata
2013	J	`jnl`	Self-Reconfigurable Constant Multiplier for FPGA. ACM Trans. Reconfigurable Technol. Syst. Javier Hormigo, Gabriel Caffarena, Juan P. Oliver, Eduardo I. Boemo
2012	J	`jnl`	A study of decimal left shifters for binary numbers. Inf. Comput. Sonia González-Navarro, Javier Hormigo, Michael J. Schulte
2012	J	`jnl`	Radix-2 Multioperand and Multiformat Streaming Online Addition. IEEE Trans. Computers Julio Villalba, Tomás Lang, Javier Hormigo
2011	—	`conf`	Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers. IT Revolutions Carlos Diego Moreno-Moreno, Pilar Martínez, Francisco Bellido, Javier Hormigo, Manuel Ortiz, Francisco J. Quiles
2011	J	`jnl`	High-Speed Algorithms and Architectures for Range Reduction Computation. IEEE Trans. Very Large Scale Integr. Syst. Francisco J. Jaime, M. A. Sánchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2010	—	`conf`	CORDIC-based LMMSE equalizer for Software Defined Radio. ICSAMOS Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael J. Schulte, John Glossner
2010	J	`jnl`	Enhanced Scaling-Free CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. Francisco J. Jaime, Miguel A. Sanchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2010	—	`conf`	UCORE: Reconfigurable Platform for Educational Purposes. ReConFig Francisco J. Quiles, Manuel Ortiz, María Brox, Carlos Diego Moreno-Moreno, Javier Hormigo, Julio Villalba
2009	—	`conf`	Efficient Implementation of Carry-Save Adders in FPGAs. ASAP Javier Hormigo, Manuel Ortiz, Francisco J. Quiles, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata
2009	—	`conf`	Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator. ICECS Carlos Diego Moreno-Moreno, Francisco J. Quiles, Manuel Ortiz, María Brox, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2008	B	`conf`	New SIMD instructions set for image processing applications enhancement. ICIP Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2008	J	`jnl`	Pipelined Architecture for Additive Range Reduction. J. Signal Process. Syst. Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata
2008	C	`conf`	SIMD Enhancements for a Hough Transform Implementation. DSD Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2007	—	`conf`	Improving the Throughput of On-line Addition for Data Streams. ASAP Julio Villalba, Javier Hormigo, Tomás Lang
2006	B	`conf`	Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. FPL Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2006	—	`conf`	Pipelined Range Reduction for Floating Point Numbers. ASAP Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata
2006	J	`jnl`	SAD computation based on online arithmetic for motion estimation. Microprocess. Microsystems Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata
2005	—	`conf`	On-line Multioperand Addition Based on On-line Full Adders. ASAP Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata
2004	J	`jnl`	CORDIC Processor for Variable-Precision Interval Arithmetic. J. VLSI Signal Process. Javier Hormigo, Julio Villalba, Emilio L. Zapata
2004	A	`conf`	Evaluation of Elementary Functions Using Multimedia Features. IPDPS Gerardo Bandera, Mario A. González, Julio Villalba, Javier Hormigo, Emilio L. Zapata
2004	B	`conf`	Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. FPL Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides
2003	—	`conf`	Texture segmentation and analysis using local spectral methods. ISSPA (1) Gabriel Cristóbal, Sylvain Fischer, Manuel Forero-Vargas, Rafael Redondo, Javier Hormigo
2002	—	`conf`	Polynomial Evaluation on Multimedia Processors. ASAP Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata
2000	—	`conf`	A Hardware Algorithm for Variable-Precision Logarithm. ASAP Javier Hormigo, Julio Villalba, Michael J. Schulte
2000	A	`conf`	MMX-Like Architecture Extension to Support the Rotation Operation. IEEE International Conference on Multimedia and Expo (III) Julio Villalba, Javier Hormigo, Mario A. González, Emilio L. Zapata
1999	—	`conf`	Arithmetic Unit for the Computation of Interval Elementary Functions. EUROMICRO Javier Hormigo, Julio Villalba, Emilio L. Zapata
1999	C	`conf`	Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. IEEE Symposium on Computer Arithmetic Javier Hormigo, Julio Villalba, Emilio L. Zapata
1999	J	`jnl`	Texture segmentation through eigen-analysis of the Pseudo-Wigner distribution. Pattern Recognit. Lett. Gabriel Cristóbal, Javier Hormigo
1998	—	`conf`	A Hardware Approach to Interval Arithmetic for Sine and Cosine Functions. SCAN Javier Hormigo, Julio Villalba, Emilio L. Zapata
1998	J	`jnl`	High resolution spectral analysis of images using the pseudo-Wigner distribution. IEEE Trans. Signal Process. Javier Hormigo, Gabriel Cristóbal