Javier Diaz-Fortuny

27 papers A 2C 2Journal 3Unranked 20

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A Ring-Oscillator-based Odometer to Unveil the Actual IC Usage Time. ISCAS F. de Los Santos-Prieto, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, F. V. Fernandez
2025	—	`conf`	Investigation of Cryogenic Aging in 28 nm CMOS: Suppression of BTI and HCD in Circuits and SRAM. IRPS Javier Diaz-Fortuny, Mahdi Benkhelifa, Alexander Grill, Erik Bury, Robin Degraeve, Ben Kaczer, Hussam Amrouch
2025	A	`conf`	Transistor Aging and Circuit Reliability at Cryogenic Temperatures. DATE Javier Diaz-Fortuny, Vishal Nayar
2025	—	`conf`	When Variability Meets Security. IRPS Rafael Castro-López, Javier Diaz-Fortuny, Elisenda Roca, Francisco V. Fernández
2024	—	`conf`	Demonstration of Chip Overclock Detection by Employing Tamper-Aware Odometer Technology. IRPS Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Alex Romano-Molar, Erik Bury, Robin Degraeve, Ben Kaczer
2024	—	`conf`	Machine Learning Unleashes Aging and Self-Heating Effects: From Transistors to Full Processor (Invited Paper). IRPS Hussam Amrouch, Victor M. van Santen, Javier Diaz-Fortuny, Florian Klemme
2024	—	`conf`	Statistical Characterization of Off-State Stress Degradation in Planar HKMG nFETs Using Device Arrays. IRPS Pablo Saraza-Canflanca, Dishant Sangani, Javier Diaz-Fortuny, Stanislav Tyaginov, Georges G. E. Gielen, Erik Bury, Ben Kaczer
2023	—	`conf`	Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability. IRPS Javier Martín-Martínez, Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría
2023	—	`conf`	Improving the Tamper-Aware Odometer Concept by Enhancing Dynamic Stress Operation. IRPS Javier Diaz-Fortuny, Dishant Sangani, Pablo Saraza-Canflanca, Erik Bury, Robin Degraeve, Ben Kaczer
2023	—	`conf`	Reliability challenges in Forksheet Devices: (Invited Paper). IRPS Erik Bury, Michiel Vandemaele, Jacopo Franco, Adrian Chasin, Stanislav Tyaginov, A. Vandooren, Romain Ritzenthaler, Hans Mertens, Javier Diaz-Fortuny, N. Horiguchi, Dimitri Linten, Ben Kaczer
2023	—	`conf`	The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper). IRPS Dishant Sangani, Javier Diaz-Fortuny, Erik Bury, Ben Kaczer, Georges G. E. Gielen
2023	—	`conf`	Using dedicated device arrays for the characterization of TDDB in a scaled HK/MG technology. IRPS Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Andrea Vici, Erik Bury, Robin Degraeve, Ben Kaczer
2022	—	`conf`	A Ring-Oscillator-Based Degradation Monitor Concept with Tamper Detection Capability. IRPS Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Erik Bury, Michiel Vandemaele, Ben Kaczer, Robin Degraeve
2022	—	`conf`	A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies. IRPS Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Andrés Santana-Andreo, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2020	J	`jnl`	A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level. Integr. Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2020	J	`jnl`	Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits. IEEE Trans. Instrum. Meas. Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Francisco V. Fernández, Montserrat Nafría
2019	—	`conf`	A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices. IRPS G. Pedreira, Javier Martín-Martínez, Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría
2019	J	`jnl`	A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI. IEEE J. Solid State Circuits Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Xavier Aragonès, Enrique Barajas, Diego Mateo, Francisco V. Fernández, Montserrat Nafría
2019	A	`conf`	New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors. DATE Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca Moreno, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019	—	`conf`	TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level. SMACD Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018	—	`conf`	A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation. SMACD Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Antonio Toro-Frías, Rafael Castro-López, Javier Martín-Martínez, Elisenda Roca, Rosana Rodríguez, Francisco V. Fernández, Montserrat Nafría
2018	—	`conf`	Automated Massive RTN Characterization Using a Transistor Array Chip. SMACD Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018	C	`conf`	CMOS Characterization and Compact Modelling for Circuit Reliability Simulation. IOLTS Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2018	—	`conf`	Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models. SMACD Pablo Saraza-Canflanca, D. Malagon, Fábio Passos, A. Toro, Juan Núñez, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018	—	`conf`	Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability. IRPS Victor M. van Santen, Javier Diaz-Fortuny, Hussam Amrouch, Javier Martín-Martínez, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Jörg Henkel, Montserrat Nafría
2017	—	`conf`	A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging. SMACD Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Enrique Barajas, Xavier Aragonès, Diego Mateo
2017	—	`conf`	TARS: A toolbox for statistical reliability modeling of CMOS devices. SMACD Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández