Javier D. Bruguera

111 papers B 1C 28Misc 4Journal 52Unranked 26

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Fused FP8 Many-Terms Dot Product With Scaling and FP32 Accumulation. IEEE Trans. Computers David Raymond Lutz, Anisha Saini, Mairin Kroes, Thomas Elmer, Harsha Valsaraju, Javier D. Bruguera
2023	J	`jnl`	Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units. IEEE Trans. Computers Javier D. Bruguera
2022	C	`conf`	Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking. ARITH David M. Russinoff, Javier D. Bruguera, Cuong Chau, Mayank Manjrekar, Nicholas Pfister, Harsha Valsaraju
2022	C	`conf`	Low-Latency and High-Bandwidth Pipelined Radix-64 Division and Square Root Unit. ARITH Javier D. Bruguera
2020	J	`jnl`	Low Latency Floating-Point Division and Square Root Unit. IEEE Trans. Computers Javier D. Bruguera
2019	J	`jnl`	Guest Editors Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers Javier D. Bruguera, Florent de Dinechin
2018	C	`conf`	Radix-64 Floating-Point Divider. ARITH Javier D. Bruguera
2017	C	`ed.`	24th IEEE Symposium on Computer Arithmetic, ARITH 2017, London, United Kingdom, July 24-26, 2017 ARITH Neil Burgess, Javier D. Bruguera, Florent de Dinechin
2016	J	`jnl`	Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors. Comput. J. Lois Orosa, Javier D. Bruguera, Elisardo Antelo
2016	J	`jnl`	Hybrid terrain rendering based on the external edge primitive. Int. J. Geogr. Inf. Sci. E. G. Paredes, Margarita Amor, Montserrat Bóo, Javier D. Bruguera, Jürgen Döllner
2014	J	`jnl`	Fast Radix-10 Multiplication Using Redundant BCD Codes. IEEE Trans. Computers Álvaro Vázquez, Elisardo Antelo, Javier D. Bruguera
2014	J	`jnl`	Obtaining Accurate Error Expressions and Bounds for Floating-Point Multiplicative Algorithms. Comput. J. Daniel Piso Fernandez, Javier D. Bruguera
2014	J	`jnl`	Optimizing the representation of intervals. Sci. Comput. Program. Javier D. Bruguera
2013	J	`jnl`	High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J. Signal Process. Syst. Roberto R. Osorio, Javier D. Bruguera
2013	J	`jnl`	Iterative Algorithm and Architecture for Exponential, Logarithm, Powering, and Root Extraction. IEEE Trans. Computers Álvaro Vázquez, Javier D. Bruguera
2012	J	`jnl`	8th Conference on Real Numbers and Computers. Inf. Comput. Marc Daumas, Javier D. Bruguera
2012	J	`jnl`	Extended hybrid meshing algorithm for multiresolution terrain models. Int. J. Geogr. Inf. Sci. E. G. Paredes, Montserrat Bóo, Margarita Amor, Javier D. Bruguera, Jürgen Döllner
2012	J	`jnl`	FlexSig: Implementing flexible hardware signatures. ACM Trans. Archit. Code Optim. Lois Orosa, Elisardo Antelo, Javier D. Bruguera
2012	—	`conf`	GPU-based Visualization of Hybrid Terrain Models. GRAPP/IVAPP E. G. Paredes, Montserrat Bóo, Margarita Amor, Jürgen Döllner, Javier D. Bruguera
2011	C	`conf`	Composite Iterative Algorithm and Architecture for q-th Root Calculation. IEEE Symposium on Computer Arithmetic Álvaro Vázquez, Javier D. Bruguera
2011	J	`jnl`	Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers Javier D. Bruguera, Marius Cornea, Debjit Das Sarma
2011	J	`jnl`	Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate. IEEE Trans. Computers Daniel Piso Fernandez, Javier D. Bruguera
2009	C	`ed.`	19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009 IEEE Symposium on Computer Arithmetic Javier D. Bruguera, Marius Cornea, Debjit Das Sarma, John Harrison
2009	C	`conf`	High Performance Image Processing on a Massively Parallel Processor Array. DSD Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera
2009	C	`conf`	Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. DSD Daniel Piso Fernandez, Javier D. Bruguera
2008	C	`conf`	A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. DSD Daniel Piso Fernandez, Javier D. Bruguera
2008	J	`jnl`	A Radix-2 Digit-by-Digit Architecture for Cube Root. IEEE Trans. Computers Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi
2008	—	`conf`	An FPGA architecture for CABAC decoding in manycore systems. ASAP Roberto R. Osorio, Javier D. Bruguera
2008	—	`conf`	Forcing one-sided results in Goldschmidt algorithm. ACSCC Daniel Piso Fernandez, Javier D. Bruguera
2008	—	`conf`	Topic 10: Parallel Numerical Algorithms. Euro-Par Hans-Joachim Bungartz, Javier D. Bruguera, Peter Arbenz, Bruce Hendrickson
2007	J	`jnl`	A Digit-by-Digit Algorithm for mth Root Extraction. IEEE Trans. Computers Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro
2007	—	`conf`	Entropy Coding on a Programmable Processor Array for Multimedia SoC. ASAP Roberto R. Osorio, Javier D. Bruguera
2007	J	`jnl`	Hardware support for adaptive tessellation of Bézier surfaces based on local tests. J. Syst. Archit. F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
2006	C	`conf`	A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. DSD Roberto R. Osorio, Javier D. Bruguera
2006	C	`conf`	A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. DSD Viay Holimath, Javier D. Bruguera
2006	C	`conf`	A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. DSD Javier D. Bruguera, Roberto R. Osorio
2006	J	`jnl`	High-Throughput Architecture for H.264/AVC CABAC Compression System. IEEE Trans. Circuits Syst. Video Technol. Roberto R. Osorio, Javier D. Bruguera
2005	C	`conf`	A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. DSD Roberto R. Osorio, Javier D. Bruguera
2005	—	`conf`	Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps. WSCG (Short Papers) F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
2005	C	`conf`	Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. IEEE Symposium on Computer Arithmetic Javier D. Bruguera, Tomás Lang
2005	J	`jnl`	High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. J. VLSI Signal Process. José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
2005	J	`jnl`	High-Speed Function Approximation Using a Minimax Quadratic Interpolator. IEEE Trans. Computers José-Alejandro Piñeiro, Stuart F. Oberman, Jean-Michel Muller, Javier D. Bruguera
2004	J	`jnl`	Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. IEEE Trans. Computers José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
2004	—	`conf`	Algorithms and Hardware for Data Compression in Point Rendering Applications. WSCG (Short Papers) Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
2004	C	`conf`	Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. DSD Roberto R. Osorio, Javier D. Bruguera
2004	J	`jnl`	Floating-Point Multiply-Add-Fused with Reduced Latency. IEEE Trans. Computers Tomás Lang, Javier D. Bruguera
2003	Misc	`conf`	Adaptive Tessellation of NURBS Surfaces. WSCG F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
2003	J	`jnl`	Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. J. Syst. Archit. Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera
2003	J	`jnl`	High performance air pollution modeling for a power plant environment. Parallel Comput. María J. Martín, David E. Singh, José Carlos Mouriño, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera
2003	C	`conf`	High-Radix Iterative Algorithm for Powering Computation. IEEE Symposium on Computer Arithmetic José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
2003	J	`jnl`	Multilevel Reverse-Carry Addition: Single and Dual Adders. J. VLSI Signal Process. Javier D. Bruguera, Tomás Lang
2003	—	`conf`	On-line high-radix exponential with selection by rounding. ISCAS (4) José-Alejandro Piñeiro, Javier D. Bruguera, Milos D. Ercegovac
2003	J	`jnl`	Research Article: A GIS-embedded system to support land consolidation plans in Galicia. Int. J. Geogr. Inf. Sci. Juan Touriño, Jorge Parapar, Ramon Doallo, Marcos Boullón, Francisco F. Rivera, Javier D. Bruguera, Xesús P. González, Rafael Crecente, Carlos Álvarez
2002	C	`conf`	Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. DSD Daniel Piso Fernandez, José-Alejandro Piñeiro, Javier D. Bruguera
2002	C	`conf`	Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. ICCD José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
2002	—	`conf`	Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes. 3DPVT Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
2002	C	`conf`	Floating-Point Fused Multiply-Add with Reduced Latency. ICCD Tomás Lang, Javier D. Bruguera
2002	—	`conf`	Hardware Implementation of the Subdivision Loop Algorithm. EUROMICRO Ángel del Río, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
2002	—	`conf`	High-Radix Logarithm with Selection by Rounding. ASAP José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
2002	J	`jnl`	High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root. IEEE Trans. Computers José-Alejandro Piñeiro, Javier D. Bruguera
2001	—	`conf`	COPA: a GIS-based Tool for Land Consolidation Projects. ACM-GIS Juan Touriño, Francisco F. Rivera, Carlos Álvarez, Cesar M. Dans, Jorge Parapar, Ramon Doallo, Marcos Boullón, Javier D. Bruguera, Rafael Crecente, Xesús P. González
2001	C	`conf`	FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. DSD José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller
2001	C	`conf`	Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. IEEE Symposium on Computer Arithmetic José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller
2001	B	`conf`	Implementation of a NURBS to Bézier Conversor with Constant Latency. FPL Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera
2001	J	`jnl`	Multilevel reverse most-significant carry computation. IEEE Trans. Very Large Scale Integr. Syst. Javier D. Bruguera, Tomás Lang
2001	—	`conf`	Parallelization of the STEM-II Air Quality Model. HPCN Europe José Carlos Mouriño, David E. Singh, María J. Martín, J. M. Eiroa, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera
2001	—	`conf`	The STEM-II Air Quality Model on a Distributed Memory System. ICPP Workshops José Carlos Mouriño, María J. Martín, Ramon Doallo, David E. Singh, Francisco F. Rivera, Javier D. Bruguera
2001	C	`conf`	Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. IEEE Symposium on Computer Arithmetic Javier D. Bruguera, Tomás Lang
2000	—	`conf`	Architectures for arithmetic coding in image compression. EUSIPCO Roberto R. Osorio, Javier D. Bruguera
2000	C	`conf`	Multilevel Reverse-Carry Adder. ICCD Javier D. Bruguera, Tomás Lang
2000	—	`conf`	Parallel Architecture for Conversion of NURBS Curves to Bézier Curves. EUROMICRO Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera
2000	C	`conf`	VLSI systolic array architecture for the lattice structure of the discrete wavelet transform. ISCAS Carlos E. Cabrera Reyes, Javier D. Bruguera
2000	J	`jnl`	Very-High Radix CORDIC Rotation Based on Selection by Rounding. J. VLSI Signal Process. Elisardo Antelo, Tomás Lang, Javier D. Bruguera
2000	J	`jnl`	Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. IEEE Trans. Computers Elisardo Antelo, Tomás Lang, Javier D. Bruguera
1999	J	`jnl`	Leading-One Prediction with Concurrent Position Correction. IEEE Trans. Computers Javier D. Bruguera, Tomás Lang
1999	C	`conf`	Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. ICCD Tomás Lang, Javier D. Bruguera
1999	—	`conf`	New model for arithmetic coding/decoding of multilevel images based on a cache memory. ICECS Roberto R. Osorio, Javier D. Bruguera
1999	C	`conf`	Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. IEEE Symposium on Computer Arithmetic Elisardo Antelo, Tomás Lang, Javier D. Bruguera
1998	J	`jnl`	A novel design of a two operand normalization circuit. IEEE Trans. Very Large Scale Integr. Syst. Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata
1998	—	`conf`	Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. EUROMICRO Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera
1998	J	`jnl`	Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. IEEE Trans. Computers Elisardo Antelo, Tomás Lang, Javier D. Bruguera
1998	C	`conf`	Leading-one prediction scheme for latency improvement in single datapath floating-point adders. ICCD Javier D. Bruguera, Tomás Lang
1998	J	`jnl`	Radix-4 Vectoring CORDIC Algorithm and Architectures. J. VLSI Signal Process. Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
1997	—	`conf`	A VLSI implementation of an arithmetic coder for image compression. EUROMICRO Mercedes Peón, Roberto R. Osorio, Javier D. Bruguera
1997	J	`jnl`	Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. IEEE Trans. Computers Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Emilio L. Zapata
1997	J	`jnl`	High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata
1997	J	`jnl`	High-performance VLSI architecture for the Viterbi algorithm. IEEE Trans. Commun. Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata
1997	J	`jnl`	Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures. J. VLSI Signal Process. Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
1997	—	`conf`	New arithmetic coder/decoder architectures based on pipelining. ASAP Roberto R. Osorio, Javier D. Bruguera
1997	Misc	`conf`	VLSI implementation of an area-efficient architecture for the Viterbi algorithm. ICASSP Carlos Cabrera, Montserrat Bóo, Javier D. Bruguera
1996	J	`jnl`	Cordic based parallel/pipelined architecture for the Hough transform. J. VLSI Signal Process. Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata
1996	—	`conf`	High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata
1996	—	`conf`	High performance VLSI architecture for the trellis coded quantization. ICIP (2) Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
1996	—	`conf`	High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. ASAP Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
1996	—	`conf`	Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
1996	J	`jnl`	Unified Mixed Radix 2-4 Redundant CORDIC Processor. IEEE Trans. Computers Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata
1995	Misc	`conf`	2-D DCT using on-line arithmetic. ICASSP Javier D. Bruguera, Tomás Lang
1995	J	`jnl`	A Parallel Architecture for the Self-Sorting FFT Algorithm. J. Parallel Distributed Comput. Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
1995	—	`conf`	CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
1995	—	`conf`	Digit On-line Large Radix CORDIC Rotator. ASAP Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
1995	C	`conf`	Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
1994	J	`jnl`	Parallel Architecture for Fast Transforms with Trigonometric Kernel. IEEE Trans. Parallel Distributed Syst. Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata
1993	J	`jnl`	Design of a Pipelined Radix 4 CORDIC Processor. Parallel Comput. Javier D. Bruguera, Elisardo Antelo, Emilio L. Zapata
1992	J	`jnl`	Image reconstruction on hypercube computers: Application to electron microscopy. Signal Process. Emilio L. Zapata, Ignacio Benavides, Francisco F. Rivera, Javier D. Bruguera, Tomás F. Pena, José María Carazo
1991	Misc	`conf`	Design of a constant geometry fast Hartley transformer. ICASSP Francisco Argüello, Ramon Doallo, Javier D. Bruguera, Emilio L. Zapata
1990	J	`jnl`	A reliability model for multiprocessor networks with degradable nodes. Microprocessing and Microprogramming Javier D. Bruguera, Emilio L. Zapata, Oscar G. Plata
1990	J	`jnl`	ACLE: A Software Package for SIMD Computer Simulation. Comput. J. Oscar G. Plata, Javier D. Bruguera, Francisco F. Rivera, Ramon Doallo, Emilio L. Zapata
1990	J	`jnl`	Gaussian elimination with pivoting on hypercubes. Parallel Comput. Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera, Emilio L. Zapata, Richard L. Peskin
1990	J	`jnl`	Multidimensional fast Hartley transform onto SIMD hypercubes. Microprocessing and Microprogramming Emilio L. Zapata, Francisco Argüello, Francisco Fernandez Rivera, Javier D. Bruguera
1990	J	`jnl`	Parallel quadrant interlocking factorization on hypercube computers. Parallel Comput. Inmaculada García, Juan Julián Merelo Guervós, Javier D. Bruguera, Emilio L. Zapata
1989	J	`jnl`	A parallel markovian model reliability algorithm for hypercube networks. Microprocessing and Microprogramming Emilio L. Zapata, Javier D. Bruguera, Oscar G. Plata, Francisco F. Rivera