Jaushin Lee - RankMe

14 papers A* 1A 5Misc 2Journal 4Unranked 1

Year	Rank	Type	Title / Venue / Authors
1996	J	`jnl`	Hierarchical test generation under architectural level functional constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaushin Lee, Janak H. Patel
1994	J	`jnl`	Addressing design for testability at the architectural level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vivek Chickermane, Jaushin Lee, Janak H. Patel
1994	J	`jnl`	Architectural level test generation for microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaushin Lee, Janak H. Patel
1993	J	`jnl`	An architectural level test generator based on nonlinear equation solving. J. Electron. Test. Jaushin Lee, Janak H. Patel
1993	Misc	`conf`	Impact of high level functional constraints on testability. VTS Jaushin Lee, Vivek Chickermane, Janak H. Patel
1993	Misc	`conf`	Testability analysis based on structural and behavioral information. VTS Jaushin Lee, Janak H. Patel
1992	A	`conf`	A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD Vivek Chickermane, Jaushin Lee, Janak H. Patel
1992	A	`conf`	An Instruction Sequence Assembling Methodology for Testing Microprocessors. ITC Jaushin Lee, Janak H. Patel
1992	—	`—`	Architectural Level Test Generation and Fault Simulation Jaushin Lee
1992	A	`conf`	Design for Testability Using Architectural Descriptions. ITC Vivek Chickermane, Jaushin Lee, Janak H. Patel
1992	A*	`conf`	Hierarchical Test Generation under Intensive Global Functional Constraints. DAC Jaushin Lee, Janak H. Patel
1991	A	`conf`	A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. ICCAD Jaushin Lee, Janak H. Patel
1991	A	`conf`	ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. ITC Jaushin Lee, Janak H. Patel
1991	—	`conf`	An Architectural Level Test Generator for a Hierarchical Design Environment. FTCS Jaushin Lee, Janak H. Patel