Jaume Segura - RankMe

94 papers A* 1A 15B 3C 8Misc 5Journal 37Unranked 25

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A 164-dBΩ Transimpedance Amplifier for Monolithic CMOS-MEMS Oscillators in Biosensing Applications. IEEE Access Rafel Perelló-Roig, Salvador Barceló, Jaume Verd, Sebastià A. Bota, Jaume Segura
2024	J	`jnl`	A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. CoRR Gabriel Torrens, Bartomeu Alorda, Cristian Carmona, Daniel Malagón-Periánez, Jaume Segura, Sebastià Antoni Bota
2024	—	`conf`	Design Guidelines for β-Multiplier Current Reference Circuits. DCIS Sebastià A. Bota, Rafel Perelló, Salvador Barceló, Ivan de Paúl, Jaume Segura, Jaume Verd
2024	J	`jnl`	Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations. J. Electron. Test. Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura
2024	J	`jnl`	SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results. CoRR Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastià A. Bota, Jaume Segura
2024	J	`jnl`	Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment. CoRR Daniel Malagón, Gabriel Torrens, Jaume Segura, Sebastià A. Bota
2023	—	`conf`	A Compact Double-Exponential Circuit for Single Event Transient Emulation. DCIS Sebastià A. Bota, Salvador Barceló, Gabriel Torrens, Rafel Perelló, Jaume Verd, Ivan de Paúl, Jaume Segura
2022	—	`conf`	Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations. LATS Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas, Jaume Segura
2022	—	`conf`	Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring. IEEE SENSORS Rafel Perelló-Roig, Francisca Orvay, Ivan de Paúl, Jaume Verd, Sebastià A. Bota, Jaume Segura
2020	J	`jnl`	Impact of Fluid Flow on CMOS-MEMS Resonators Oriented to Gas Sensing. Sensors Rafel Perelló-Roig, Jaume Verd, Sebastià A. Bota, Jaume Segura
2019	J	`jnl`	A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. IEEE Trans. Emerg. Top. Comput. Gabriel Torrens, Bartomeu Alorda, Cristian Carmona, Daniel Malagón-Periánez, Jaume Segura, Sebastià A. Bota
2018	C	`conf`	Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator. ISCAS Joan Barceló, Ivan de Paúl, Sebastià A. Bota, Jaume Segura, Jaume Verd
2018	C	`conf`	Frequency Fluctuations in CMOS-MEMS Oscillators: Towards the Thermomechanical Limit. ISCAS Rafel Perelló-Roig, Jaume Verd, Sebastià A. Bota, Jaume Segura
2018	J	`jnl`	Thermomechanical Noise Characterization in Fully Monolithic CMOS-MEMS Resonators. Sensors Rafel Perelló-Roig, Jaume Verd, Sebastià A. Bota, Jaume Segura
2017	—	`conf`	Cantilever NEMS relay-based SRAM devices for enhanced reliability. DTIS Sebastià A. Bota, Jaume Verd, Joan Barceló, Xavier Gili, Bartomeu Alorda, Gabriel Torrens, Carol de Benito, Jaume Segura
2017	—	`conf`	Integrated microelectromechanical systems in the More than Moore era. DTIS Jaume Segura
2017	J	`jnl`	Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources. Microelectron. Reliab. Daniel Malagón, Sebastià A. Bota, Gabriel Torrens, Xavier Gili, Javier Praena, B. Fernández, Miguel Macías, José Manuel Quesada, Carlos Guerrero Sanchez, María del Carmen Jiménez-Ramos, Javier García López, José Luis Merino, Jaume Segura
2017	—	`conf`	Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells. SMACD Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Gabriel Torrens, Sebastià A. Bota, Jaume Segura, Francesc Moll, Antonio Rubio
2016	J	`jnl`	Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective. Commun. Nonlinear Sci. Numer. Simul. Joan Barceló, José Luis Rosselló, Sebastià A. Bota, Jaume Segura, Jaume Verd
2016	J	`jnl`	Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. J. Electron. Test. Hector Villacorta, Jaume Segura, Víctor H. Champac
2015	—	`conf`	Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. LATS Hector Villacorta, Roberto Gómez, Sebastià A. Bota, Jaume Segura, Víctor H. Champac
2015	J	`jnl`	Low V Microelectron. J. Hector Villacorta, Jose Luis Garcia-Gervacio, Jaume Segura, Víctor H. Champac
2014	J	`jnl`	Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells. Microelectron. Reliab. Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura
2014	—	`conf`	Analysis of fin height on FinFET SRAM cell hardening. MWSCAS Hector Villacorta, Jaume Segura, Sebastià A. Bota, Víctor H. Champac
2014	J	`jnl`	Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions. IEEE Trans. Very Large Scale Integr. Syst. Salvador Barceló, Xavier Gili, Sebastià A. Bota, Jaume Segura
2013	J	`jnl`	Alternate characterization technique for static random-access memory static noise margin determination. Int. J. Circuit Theory Appl. José Luis Merino, Sebastià Antoni Bota, Rodrigo Picos, Jaume Segura
2013	—	`conf`	Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias. LATW Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota, Jaime Martínez-Castillo, Jaume Segura
2013	J	`jnl`	Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths. IEEE Des. Test Hector Villacorta, Charles F. Hawkins, Víctor H. Champac, Jaume Segura, Roberto Gómez
2012	J	`jnl`	Resistive bridge defect detection enhancement under parameter variations combining Low V Microelectron. Reliab. Hector Villacorta, Víctor H. Champac, Sebastià A. Bota, Jaume Segura
2012	J	`jnl`	Testing of Stuck-Open Faults in Nanometer Technologies. IEEE Des. Test Comput. Víctor H. Champac, Julio Vazquez Hernandez, Salvador Barceló, Roberto Gómez, Chuck Hawkins, Jaume Segura
2011	J	`jnl`	8T vs. 6T SRAM cell radiation robustness: A comparative analysis. Microelectron. Reliab. Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura
2011	A	`conf`	An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation. DATE Salvador Barceló, Xavier Gili, Sebastià A. Bota, Jaume Segura
2011	A	`conf`	Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation. DATE Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura
2010	C	`conf`	Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories. IOLTS Sebastià A. Bota, Gabriel Torrens, Bartomeu Alorda, Jaume Verd, Jaume Segura
2010	J	`jnl`	Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. IEEE Trans. Circuits Syst. II Express Briefs Gabriel Torrens, Bartomeu Alorda, Salvador Barceló, José Luis Rosselló, Sebastià A. Bota, Jaume Segura
2010	—	`conf`	Reliability analysis of small delay defects in vias located in signal paths. LATW Hector Villacorta, Víctor H. Champac, Chuck Hawkins, Jaume Segura
2010	A	`conf`	Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. DATE Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura
2009	—	`conf`	A modern look at the CMOS stuck-open fault. LATW Roberto Gómez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
2009	Misc	`conf`	Stuck-Open Fault Leakage and Testing in Nanometer Technologies. VTS Julio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura
2008	B	`conf`	Using stochastic logic for efficient pattern recognition analysis. IJCNN José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura
2007	J	`jnl`	A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs CoRR José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
2007	J	`jnl`	Charge-based testing BIST for embedded memories. IET Comput. Digit. Tech. Bartomeu Alorda, Ivan de Paúl, Jaume Segura
2007	A	`conf`	Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. DATE José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
2007	C	`conf`	Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. IOLTS X. Cano, Sebastià A. Bota, Ricardo Graciani Diaz, David Gascon, A. Herms, Albert Comerma, Jaume Segura, Lluís Garrido
2007	J	`jnl`	Smart Temperature Sensor for Thermal Testing of Cell-Based ICs CoRR Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
2006	B	`conf`	A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura
2006	A	`conf`	A compact model to identify delay faults due to crosstalk. DATE José Luis Rosselló, Jaume Segura
2006	C	`conf`	CMOS Testing at the End of the Roadmap: Challenges and Opportunities. DDECS Jaume Segura
2006	J	`jnl`	Impact of Thermal Gradients on Clock Skew and Testing. IEEE Des. Test Comput. Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura
2006	—	`conf`	Leakage Power Characterization Considering Process Variations. PATMOS José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
2006	Misc	`conf`	Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. VTS Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
2005	A	`conf`	A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. DATE José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
2005	C	`conf`	A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. IOLTS Bartomeu Alorda, Sebastià A. Bota, Jaume Segura
2005	J	`jnl`	A compact gate-level energy and delay model of dynamic CMOS gates. IEEE Trans. Circuits Syst. II Express Briefs José Luis Rosselló, Carol de Benito, Jaume Segura
2005	—	`conf`	Compact Static Power Model of Complex CMOS Gates. PATMOS José Luis Rosselló, Sebastià A. Bota, Jaume Segura
2005	A	`conf`	Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. DATE Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
2005	B	`conf`	The anatomy of nanometer timing failures. ETS Chuck Hawkins, Jaume Segura
2004	C	`conf`	A BIST-based Charge Analysis for Embedded Memories. IOLTS Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura
2004	A	`conf`	A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. DATE José Luis Rosselló, Jaume Segura
2004	J	`jnl`	A Two-Level Power-Grid Model for Transient Current Testing Evaluation. J. Electron. Test. Bartomeu Alorda, Vincent Canals, Jaume Segura
2004	A	`conf`	Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. ITC Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi
2003	J	`jnl`	A BICS for CMOS OpAmps by Monitoring the Supply Current Peak. J. Electron. Test. Joan Font, J. Ginard, Rodrigo Picos, Eugeni Isern, Jaume Segura, Miquel Roca, Eugenio García
2003	—	`conf`	A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. PATMOS José Luis Rosselló, Jaume Segura
2003	—	`conf`	A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect. DFT Charles F. Hawkins, Ali Keshavarzi, Jaume Segura
2003	C	`conf`	An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. IOLTS Bartomeu Alorda, Jaume Segura
2003	A	`conf`	CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. ITC Bartomeu Alorda, Brad Bloechel, Ali Keshavarzi, Jaume Segura
2003	—	`conf`	CMOS IC nanometer technology failure mechanisms. CICC Charles F. Hawkins, Ali Keshavarzi, Jaume Segura
2003	J	`jnl`	Structural RFIC device testing through built-in thermal monitoring. IEEE Commun. Mag. Josep Altet, Antonio J. Rubio, José Luis Rosselló, Jaume Segura
2002	—	`conf`	A BICS for CMOS Opamps by Monitoring the Supply Current Peak. IOLTW Joan Font, J. Ginard, Eugeni Isern, Miquel Roca, Jaume Segura, Eugenio García
2002	—	`conf`	A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. PATMOS José Luis Rosselló, Jaume Segura
2002	A*	`conf`	A novel wavelet transform based transient current analysis for fault detection and localization. DAC Swarup Bhunia, Kaushik Roy, Jaume Segura
2002	—	`conf`	An Off-Chip Sensor Circuit for On-Line Transient Current Testing. IOLTW Bartomeu Alorda, André Ivanov, Jaume Segura
2002	Misc	`conf`	Challenges in Nanometric Technology Scaling: Trends and Projections. VTS Jaume Segura, Vivek De, Ali Keshavarzi
2002	A	`conf`	Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. ITC Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura
2002	J	`jnl`	Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José Luis Rosselló, Jaume Segura
2002	A	`conf`	GHz Testing and Its Fuzzy Targets. ITC Chuck Hawkins, Jaume Segura
2002	J	`jnl`	Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era. IEEE Des. Test Comput. Jaume Segura, Peter C. Maxwell
2002	A	`conf`	Parametric Failures in CMOS ICs - A Defect-Based Analysis. ITC Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins
2001	Misc	`conf`	Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. VTS Ivan de Paúl, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden
2001	A	`conf`	Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. ICCAD José Luis Rosselló, Jaume Segura
2000	J	`jnl`	Experimental Results on BIC Sensors for Transient Current Testing. J. Electron. Test. Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugenio García-Moreno
2000	—	`conf`	On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. IOLTW Bartomeu Alorda, Ivan de Paúl, Jaume Segura, T. Miller
2000	—	`conf`	Transient Current Monitoring Using a Current-to-Frequency Converter. LATW Rodrigo Picos, J. Colom, Miquel Roca, Eugeni Isern, Jaume Segura, Oscar Calvo, Eugenio García-Moreno
1999	Misc	`conf`	Analyzing the Need for ATPG Targeting GOS Defects. VTS Eugeni Isern, Miquel Roca, Jaume Segura
1999	—	`conf`	Experimental results on BIC sensors for transient current testing. ETW Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugenio García-Moreno
1999	J	`jnl`	Test and Reliability: Partners in IC Manufacturing, Part 1. IEEE Des. Test Comput. Charles F. Hawkins, Jaume Segura
1999	J	`jnl`	Test and Reliability: Partners in IC Manufacturing, Part 2. IEEE Des. Test Comput. Charles F. Hawkins, Jaume Segura, Jerry M. Soden, Ted Dellin
1998	J	`jnl`	A variable threshold voltage inverter for CMOS programmable logic circuits. IEEE J. Solid State Circuits Jaume Segura, José Luis Rosselló, J. Morra, H. Sigg
1998	J	`jnl`	Clocked Dosimeter Compatible with Digital CMOS Technology. J. Electron. Test. Eugenio García-Moreno, Benjamín Iñíguez, Miquel Roca, Jaume Segura, Eugeni Isern
1998	—	`conf`	Integrated Cmos Linear Dosimeter. SBCCI Oscar Calvo, M. González, C. Romero, Eugenio García-Moreno, Eugeni Isern, Miquel Roca, Jaume Segura
1997	J	`jnl`	A detailed analysis of CMOS SRAM's with gate oxide short defects. IEEE J. Solid State Circuits Jaume Segura, Antonio Rubio
1996	J	`jnl`	A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors. J. Electron. Test. Jaume Segura, Carol de Benito, Antonio Rubio, Charles F. Hawkins
1995	A	`conf`	A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level. ITC Jaume Segura, Carol de Benito, Antonio Rubio, Charles F. Hawkins
1995	—	`conf`	A built-in quiescent current monitor for CMOS VLSI circuits. ED&TC Antonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo, P. De Pauw, Jaume Segura