Jau-Ji Jou

16 papers C 2Journal 4Unranked 10
YearRankTypeTitle / Venue / Authors
2025 J jnl
Design and Verification of a 53-Gb/s PAM-4 Cooled DFB-LD TOSA Employing Cost-Effective TO-CAN Package.
IEEE Access
Wahyu Hidayat, Pei-Hao Tseng, Jia-Hong Liu, Jau-Ji Jou
2025 J jnl
Real-Time Monitoring of High-Speed Signal Quality Using Asynchronous Sampling, Amplitude Sorting, and Artificial Neural Network and Its FPGA Implementation.
Int. J. Circuit Theory Appl.
Jau-Ji Jou, Chun-Liang Yang, Chih-lung Tseng, Chun-Chen Yao, Jun-Yuan Zheng
2023 — conf
The Abnormal Events Detection System by Feature Enhancement-Based Deep Learning Network.
GCCE
Chao-Ho Chen, Tsong-Yi Chen, Yong-Lin Chen, Bing-Hong Liu, Jau-Ji Jou, Cheng-Kang Wen
2022 J jnl
32-Gb/s NRZ and 40-Gb/s PAM-4 Transimpedance Amplifier Paralleling with a Differentiator for Bandwidth Enhancement in 90-nm CMOS Technology.
Circuits Syst. Signal Process.
Jau-Ji Jou, Tien-Tsorng Shih, Hao-Wen Hsu
2022 — conf
An Algorithm Design for Minimum-Latency Scheduling in Multiple-Data-Type Multi-Channel WSNs.
GCCE
Vinh V. Le, Dung H. P. Nguyen, Bing-Hong Liu, Shao-I Chu, Chih-Yuan Lien, Jau-Ji Jou
2022 — conf
The Study of 60 GHz Wideband Conductor-Backed Coplanar Waveguide on a TGV Substrate.
GCCE
C. L. Chiu, Ting-Rong Chen, Chia-Wei Lee, Jau-Ji Jou
2021 — conf
A 40-Gb/s NRZ Inductorless Transimpedance Amplifier in a 0.18-μm SiGe BiCMOS Technology.
ISPACS
Hao-Wen Hsu, Xuan-Yi Ye, Jau-Ji Jou, Tien-Tsorng Shih
2021 — conf
Performance Monitoring of High-Speed NRZ Signals Using Machine Learning Techniques.
ISPACS
Chun-Chen Yao, Jun-Yuan Zheng, Jau-Ji Jou, Chun-Liang Yang
2019 — conf
25 Gb/s NRZ and 50 Gb/s PAM-4 Transimpedance Amplifier with Active Feedback and Equalization in 90 nm CMOS Technology.
ICETE (1)
Hao-Wen Hsu, Chih-Chen Peng, Jau-Ji Jou, Tien-Tsorng Shih, Yaw-Dung Wu, Shao-I Chu, Chih-Yuan Lien, Bing-Hong Liu
2019 C conf
Design of High-Speed Optical Receiver Module for 160Gb/s NRZ and 200Gb/s PAM4 Transmissions.
ISCAS
Jian-Yu Lai, Chuan-Yu Liao, Jau-Ji Jou, Tien-Tsorng Shih, Po-Jui Chiang
2019 C conf
Design of a 25-Gb/s PAM-4 VCSEL Diode Driver with an Equalizer in 90-nm CMOS Technology.
ISCAS
Tsung-Yen Wu, Jau-Ji Jou, Tien-Tsorng Shih, Po-Jui Chiang, Yaw-Dung Wu
2017 — conf
Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link.
OFC
Hsuan-Yun Kao, Cheng-Ting Tsai, Chun-Yen Pong, Shan-Fong Liang, Zu-Kai Weng, Yu-Chieh Chi, Hao-Chung Kuo, Jian Jang Huang, Tai-Cheng Lee, Tien-Tsorng Shih, Jau-Ji Jou, Wood-Hi Cheng, Chao-Hsin Wu, Gong-Ru Lin
2017 — conf
High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers.
ISOCC
Chih-Chen Peng, Jau-Ji Jou, Tien-Tsorng Shih, Chien-Liang Chiu
2017 — conf
Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology.
ISOCC
Chi-Hsien Wu, Jau-Ji Jou, Hsin-Wen Ting, Shao-I Chu, Bing-Hong Liu
2016 — conf
Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter.
ISOCC
Hong-Jhih Chen, Jau-Ji Jou, Tien-Tsorng Shih
2002 J jnl
Application of SPICE simulation to study WDM and SCM systems using EDFAs with chirping.
IEEE Trans. Educ.
Jau-Ji Jou, Cheng-Kuang Liu