Jatindra Kumar Deka

42 papers A 1B 9C 6Misc 1Journal 11Unranked 14

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Incomplete Testing of SOC. J. Electron. Test. Kunwer Mrityunjay Singh, Jatindra Kumar Deka, Santosh Biswas
2021	C	`conf`	ATPG for Incomplete Testing of SOC Considering Bridging Faults. TENCON Kunwer Mrityunjay Singh, Santosh Biswas, Jatindra Kumar Deka
2021	—	`conf`	Conversion of Virtual Lab Experiments using FOSS: A Case Study of Virtual Labs by NMEICT. TALE Nanu Alan Kachari, Santosh Biswas, Jatindra Kumar Deka
2021	J	`jnl`	Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement. J. Electron. Test. Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka
2021	B	`conf`	Selective Fault-Masking for Improving Yield and Performance of On-Chip Networks. SMC Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2020	C	`conf`	A Fault Detection Scheme for Reversible Circuits using -Ve Control k-CNOT Based Circuit. TENCON Mousum Handique, Jatindra Kumar Deka, Santosh Biswas
2020	J	`jnl`	An Efficient Test Set Construction Scheme for Multiple Missing-Gate Faults in Reversible Circuits. J. Electron. Test. Mousum Handique, Jatindra Kumar Deka, Santosh Biswas
2020	—	`conf`	Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis. VDAT Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka
2020	—	`conf`	Improving Reliability in Spidergon Network on Chip-Microprocessors. MWSCAS Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2020	—	`conf`	Locating Open-Channels in Octagon Networks on Chip-Microprocessors. ISVLSI Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
2020	C	`conf`	Maximizing Yield through Retesting of Rejected Circuits using Approximation Technique. TENCON Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka
2020	—	`conf`	Reliability Monitoring in a Smart NoC Component. ICECS Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2020	B	`conf`	Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels. SMC Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
2019	J	`jnl`	A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip. J. Electron. Test. Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
2019	J	`jnl`	Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip. ACM Trans. Design Autom. Electr. Syst. Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya
2019	—	`conf`	Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application. PReMI (2) Sisir Kumar Jena, Santosh Biswas, Jatindra Kumar Deka
2019	J	`jnl`	Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions. J. Electron. Test. Mousum Handique, Santosh Biswas, Jatindra Kumar Deka
2018	J	`jnl`	On-Line Analysis of Stuck-at Faults in On-Chip Network Interconnects. J. Circuits Syst. Comput. Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2018	J	`jnl`	Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
2017	J	`jnl`	A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks. J. Electron. Test. Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2017	A	`conf`	Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs. DATE Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2016	—	`conf`	A Reliability-Aware Topology-Agnostic Test Scheme for Detecting, and Diagnosing Interconnect Shorts in On-chip Networks. HPCC/SmartCity/DSS Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
2016	B	`conf`	A topology-agnostic test model for link shorts in on-chip networks. SMC Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya
2016	C	`conf`	An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCs. IOLTS Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
2016	C	`conf`	An on-line test solution for addressing interconnect shorts in on-chip networks. IOLTS Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2016	B	`conf`	Detecting and diagnosing open faults in NoC channels on activation of diagonal nodes. SMC Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
2016	B	`conf`	On-line detection and diagnosis of stuck-at faults in channels of NoC-based systems. SMC Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas, Bhargab B. Bhattacharya
2016	B	`conf`	One poison is antidote against another poison. SMC Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya
2016	B	`conf`	Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in On-chip Networks. MASCOTS Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2016	—	`conf`	When Clustering Shows Optimality towards Analyzing Stuck-at Faults in Channels of On-chip Networks. HPCC/SmartCity/DSS Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2015	—	`conf`	A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects. MED Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
2015	B	`conf`	An Optimal Diagnosis of NoC Interconnects on Activation of Diagonal Routers. SMC Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
2015	B	`conf`	Directed Symbolic Execution for VLSI Circuits. SMC Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2015	—	`conf`	Reliability on Top of Best Effort Delivery: Maximal Connectivity Test on NoC Interconnects. COMPUTE Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas
2014	—	`conf`	Detection of faulty interswitch links in 2-D mesh network-on-chips. IEEE ANTS Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka
2010	—	`conf`	Fair diagnosability in PN-based DES models. ICCA Khan Ajoy, Kushagra Misra, Santosh Biswas, Jatindra Kumar Deka, Hemangee K. Kapoor
2005	—	`conf`	Variable Ordering of BDDs using Genetic Algorithm. IICAI Moi Riba, Jatindra Kumar Deka
2003	C	`conf`	Reasoning about Extremal Properties of Events. TIME Jatindra Kumar Deka
2001	—	`conf`	Abstractions for model checking of event timings. ISCAS (5) Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti
2001	J	`jnl`	Min-max Computation Tree Logic. Artif. Intell. Pallab Dasgupta, P. P. Chakrabarti, Jatindra Kumar Deka, Sriram Sankaranarayanan
2000	J	`jnl`	Model checking on timed-event structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pallab Dasgupta, Jatindra Kumar Deka, Partha Pratim Chakrabarti
1999	Misc	`conf`	An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. VLSI Design Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti