Jason Helge Anderson

143 papers A* 4A 27B 20C 4Misc 8Journal 25Unranked 54

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	ARCS: Architecture-Responsive CGRA Scheduling. ASP-DAC Omar Ragheb, Jason Helge Anderson
2025	A	`conf`	FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. FPGA Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne
2025	—	`conf`	RAAP-CGRA: Placement for CGRAs with Restricted Routing Architectures. IPDPS (Workshops) Anh Nguyen, Sebastian Czyrny, Takahide Yoshikawa, Jason Helge Anderson
2025	—	`conf`	Systolic Array-Based Matrix Multiplication and Reduction on Elastic CGRAs. HEART Aditya Srichandan, Omar Ragheb, Jason Helge Anderson
2024	—	`conf`	CAD Techniques for NoC-Connected Multi-CGRA Systems. HEART Haoran Wei, Omkar Bhilare, Hamas Waqar, Jason Helge Anderson
2024	—	`conf`	CGRA-ME 2.0: A Research Framework for Next-Generation CGRA Architectures and CAD. IPDPS (Workshops) Omar Ragheb, Stephen Wicklund, Matthew Walker, Rami Beidas, Adham Ragab, TianYi Yu, Jason Helge Anderson
2024	A*	`conf`	CLUMAP: Clustered Mapper for CGRAs with Predication. DAC Omar Ragheb, Jason Helge Anderson
2024	—	`conf`	MLIR-to-CGRA: A Versatile MLIR-Based Compiler Framework for CGRAs. ASAP TianYi Yu, Omar Ragheb, Stephen Wicklund, Jason Helge Anderson
2024	Misc	`conf`	Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams. FCCM Rami Beidas, Jason Helge Anderson
2024	—	`conf`	Raising Compute Density of Molecular Dynamics Simulation Through Approximate Memoization. ASAP Salim Khemira, Xinyuan Wang, Anh Nguyen, Yutaka Tamiya, Makoto Taiji, Takahide Yoshikawa, Jason Helge Anderson
2023	—	`conf`	Area-Driven FPGA Logic Synthesis Using Reinforcement Learning. ASP-DAC Guanglei Zhou, Jason Helge Anderson
2023	B	`conf`	GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. FPL Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson
2023	—	`conf`	Statically Scheduled vs. Elastic CGRA Architectures: Impact on Mapping Feasibility. IPDPS Workshops Omar Ragheb, Rami Beidas, Jason Helge Anderson
2022	—	`conf`	CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams. ASP-DAC Rami Beidas, Jason Helge Anderson
2022	J	`jnl`	Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides
2022	—	`conf`	Elastic Multi-Context CGRAs. IPDPS Workshops Omar Ragheb, TianYi Yu, Rami Beidas, Jason Helge Anderson
2022	B	`conf`	Modeling and Exploration of Elastic CGRAs. FPL Omar Ragheb, TianYi Yu, David Ma, Jason Helge Anderson
2022	—	`conf`	Streaming Accuracy: Characterizing Early Termination in Stochastic Computing. ASP-DAC Hsuan Hsiao, Joshua San Miguel, Jason Helge Anderson
2021	C	`conf`	An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems. DSD Xiaoyi Ling, Takahiro Notsu, Jason Helge Anderson
2021	—	`conf`	CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper). ASAP Jason Helge Anderson, Rami Beidas, Vimal Chacko, Hsuan Hsiao, Xiaoyi Ling, Omar Ragheb, Xinyuan Wang, TianYi Yu
2021	—	`conf`	Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays. ASAP Xinyuan Wang, TianYi Yu, Hsuan Hsiao, Jason Helge Anderson
2021	—	`conf`	High-Level Synthesis of Transactional Memory. ASP-DAC Omar Ragheb, Jason Helge Anderson
2021	B	`conf`	Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation. FPL Jin Hee Kim, Jason Helge Anderson
2021	—	`conf`	Power, Performance and Area Consequences of Multi-Context Support in CGRAs. ASAP Vimal Chacko, Jason Helge Anderson
2021	—	`conf`	Profiling-Based Control-Flow Reduction in High-Level Synthesis. FPT Austin Liolli, Omar Ragheb, Jason Helge Anderson
2021	—	`conf`	Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing. ASP-DAC Hsuan Hsiao, Joshua San Miguel, Yuko Hara-Azumi, Jason Helge Anderson
2020	J	`jnl`	Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2019	B	`conf`	A Dynamic Memory Allocation Library for High-Level Synthesis. FPL Nicholas V. Giamblanco, Jason Helge Anderson
2019	—	`conf`	ASAP: Automatic Sizing and Partitioning for Dynamic Memory Heaps in High-Level Synthesis. FPT Nicholas V. Giamblanco, Jason Helge Anderson
2019	A	`conf`	EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides
2019	Misc	`conf`	Generic Connectivity-Based CGRA Mapping via Integer Linear Programming. FCCM Matthew J. P. Walker, Jason Helge Anderson
2019	J	`jnl`	Generic Connectivity-Based CGRA Mapping via Integer Linear Programming. CoRR Matthew J. P. Walker, Jason Helge Anderson
2019	—	`conf`	High-Level Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing. FPT Yu Ting Chen, Jin Hee Kim, Kexin Li, Graham Hoyes, Jason Helge Anderson
2019	Misc	`conf`	Impact of FPGA Architecture on Area and Performance of CGRA Overlays. FCCM Ian Taras, Jason Helge Anderson
2019	—	`conf`	Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs. HEART Brett Grady, Jason Helge Anderson
2019	A*	`conf`	Thread Weaving: Static Resource Scheduling for Multithreaded High-Level Synthesis. DAC Hsuan Hsiao, Jason Helge Anderson
2019	—	`conf`	XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration. ASP-DAC Hyeon Uk Sim, Jason Helge Anderson, Jongeun Lee
2018	—	`conf`	Accelerating Memcached on AWS Cloud FPGAs. HEART Jongsok Choi, Ruolong Lian, Zhi Li, Andrew Canis, Jason Helge Anderson
2018	A*	`conf`	An architecture-agnostic integer linear programming approach to CGRA mapping. DAC S. Alexander Chin, Jason Helge Anderson
2018	—	`conf`	Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework. ISPD S. Alexander Chin, Kuang Ping Niu, Matthew J. P. Walker, Shizhang Yin, Alexander Mertens, Jongeun Lee, Jason Helge Anderson
2018	—	`conf`	Compact Area and Performance Modelling for CGRA Architecture Evaluation. FPT Kuang Ping Niu, Jason Helge Anderson
2018	—	`conf`	FPGA Architecture Enhancements for Efficient BNN Implementation. FPT Jin Hee Kim, Jongeun Lee, Jason Helge Anderson
2018	J	`jnl`	FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software. CoRR Jin Hee Kim, Brett Grady, Ruolong Lian, John Brothers, Jason Helge Anderson
2018	Misc	`conf`	High-Level Synthesis of FPGA Circuits with Multiple Clock Domains. FCCM Omar Ragheb, Jason Helge Anderson
2018	A	`conf`	High-level synthesis of software-customizable floating-point cores. DATE Samridhi Bansal, Hsuan Hsiao, Tomasz S. Czajkowski, Jason Helge Anderson
2018	A	`ed.`	Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018 FPGA Jason Helge Anderson, Kia Bazargan
2018	A	`conf`	Sensei: An area-reduction advisor for FPGA high-level synthesis. DATE Hsuan Hsiao, Jason Helge Anderson
2018	—	`conf`	Software-Specified FPGA Accelerators for Elementary Functions. FPT Jing Chen, Xue Liu, Jason Helge Anderson
2018	—	`conf`	Synthesizable Heterogeneous FPGA Fabrics. FPT Brett Grady, Jason Helge Anderson
2017	B	`conf`	Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software. FPL Yu Ting Chen, Jason Helge Anderson
2017	—	`conf`	CGRA-ME: A unified framework for CGRA modelling and exploration. ASAP S. Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin Hee Kim, Yuko Hara-Azumi, Jason Helge Anderson
2017	—	`conf`	FPGA-based CNN inference accelerator synthesized from multi-threaded C software. SoCC Jin Hee Kim, Brett Grady, Ruolong Lian, John Brothers, Jason Helge Anderson
2017	J	`jnl`	From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson
2017	J	`jnl`	Leveraging Unused Resources for Energy Optimization of FPGA Interconnect. IEEE Trans. Very Large Scale Integr. Syst. Safeen Huda, Jason Helge Anderson
2017	J	`jnl`	Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA Overlays. ACM Trans. Reconfigurable Technol. Syst. Charles Eric LaForest, Jason Helge Anderson
2017	A	`ed.`	Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017 FPGA Jonathan W. Greene, Jason Helge Anderson
2017	J	`jnl`	Subleq⊝: An Area-Efficient Two-Instruction-Set Computer. IEEE Embed. Syst. Lett. Noriaki Sakamoto, Tanvir Ahmed, Jason Helge Anderson, Yuko Hara-Azumi
2017	J	`jnl`	Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow. ACM Trans. Reconfigurable Technol. Syst. Jin Hee Kim, Jason Helge Anderson
2017	J	`jnl`	The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
2016	B	`ed.`	26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016 FPL Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
2016	J	`jnl`	A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels
2016	—	`conf`	A unified software approach to specify pipeline and spatial parallelism in FPGA hardware. ASAP Jongsok Choi, Ruolong Lian, Stephen Brown, Jason Helge Anderson
2016	A	`conf`	Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. DATE Jason Helge Anderson, Yuko Hara-Azumi, Shigeru Yamashita
2016	—	`conf`	High-level synthesis - the right side of history. FPT Jason Helge Anderson
2016	J	`jnl`	Hybrid LUT/Multiplexer FPGA Logic Architectures. IEEE Trans. Very Large Scale Integr. Syst. S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson
2016	—	`ch.`	LegUp High-Level Synthesis. FPGAs for Software Programmers Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Brown, Jason Helge Anderson
2016	—	`conf`	Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques. ISPD Safeen Huda, Jason Helge Anderson
2016	B	`conf`	Preface. FPL Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
2016	A	`conf`	Towards PVT-Tolerant Glitch-Free Operation in FPGAs. FPGA Safeen Huda, Jason Helge Anderson
2015	A	`conf`	Profiling-driven multi-cycling in FPGA high-level synthesis. DATE Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, Jason Helge Anderson
2015	—	`conf`	Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. FPT Jongsok Choi, Stephen Brown, Jason Helge Anderson
2015	B	`conf`	Significant papers from the first 25 years of the FPL conference. FPL Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
2015	B	`conf`	Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. FPL Jin Hee Kim, Jason Helge Anderson
2015	C	`conf`	Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC. EUC Tanvir Ahmed, Noriaki Sakamoto, Jason Helge Anderson, Yuko Hara-Azumi
2015	J	`jnl`	The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. ACM Trans. Reconfigurable Technol. Syst. Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Brown, Jason Helge Anderson
2014	—	`conf`	Approaching overhead-free execution on FPGA soft-processors. FPT Charles Eric LaForest, Jason Helge Anderson, J. Gregory Steffan
2014	C	`conf`	Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. EUC Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson
2014	—	`conf`	Design re-use for compile time reduction in FPGA high-level synthesis flows. FPT Marcel Gort, Jason Helge Anderson
2014	J	`jnl`	Introduction to the Special Issue on the 11 ACM Trans. Reconfigurable Technol. Syst. Jason Helge Anderson, Kiyoung Choi
2014	B	`conf`	Modulo SDC scheduling with recurrence minimization in high-level synthesis. FPL Andrew Canis, Stephen Dean Brown, Jason Helge Anderson
2014	Misc	`conf`	On Hard Adders and Carry Chains in FPGAs. FCCM Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2014	A	`conf`	Optimizing effective interconnect capacitance for FPGA power reduction. FPGA Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
2014	—	`conf`	Power Modeling for Heterogeneous Processors. GPGPU@ASPLOS Tahir Diop, Natalie D. Enright Jerger, Jason Helge Anderson
2014	B	`conf`	Source-level debugging for FPGA high-level synthesis. FPL Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson
2014	A	`conf`	Towards interconnect-adaptive packing for FPGAs. FPGA Jason Luu, Jonathan Rose, Jason Helge Anderson
2014	J	`jnl`	VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2013	—	`conf`	A case for hardened multiplexers in FPGAs. FPT S. Alexander Chin, Jason Helge Anderson
2013	—	`conf`	Bitwidth-optimized hardware accelerators with software fallback. FPT Ana Klimovic, Jason Helge Anderson
2013	B	`conf`	Charge recycling for power reduction in FPGA interconnect. FPL Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
2013	J	`jnl`	Combined Architecture/Algorithm Approach to Fast FPGA Routing. IEEE Trans. Very Large Scale Integr. Syst. Marcel Gort, Jason Helge Anderson
2013	B	`conf`	DistCL: A Framework for the Distributed Execution of OpenCL Kernels. MASCOTS Tahir Diop, Steven Gurfinkel, Jason Helge Anderson, Natalie D. Enright Jerger
2013	—	`conf`	From C to Blokus Duo with LegUp high-level synthesis. FPT Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Brown, Jason Helge Anderson
2013	—	`conf`	From software threads to parallel hardware in high-level synthesis for FPGAs. FPT Jongsok Choi, Stephen Brown, Jason Helge Anderson
2013	Misc	`conf`	From software to accelerators with LegUp high-level synthesis. CASES Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson
2013	A	`conf`	High-level synthesis with LegUp: a crash course for users and researchers. FPGA Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi
2013	J	`jnl`	Latch-Based Performance Optimization for Field-Programmable Gate Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bill Teng, Jason Helge Anderson
2013	—	`conf`	Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance. ReConFig Edgar Mora-Sanchez, Jason Helge Anderson
2013	J	`jnl`	LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson
2013	A	`conf`	Multi-pumping for resource reduction in FPGA high-level synthesis. DATE Andrew Canis, Jason Helge Anderson, Stephen Dean Brown
2013	—	`conf`	Range and bitmask analysis for hardware optimization in high-level synthesis. ASP-DAC Marcel Gort, Jason Helge Anderson
2013	Misc	`conf`	The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. FCCM Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Brown, Jason Helge Anderson
2012	J	`jnl`	Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Marcel Gort, Jason Helge Anderson
2012	B	`conf`	Analytical placement for heterogeneous FPGAs. FPL Marcel Gort, Jason Helge Anderson
2012	A	`conf`	Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power. FPGA Warren Wai-Kit Shum, Jason Helge Anderson
2012	J	`jnl`	FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings
2012	C	`conf`	FPGA power reduction by guarded evaluation considering physical information. VLSI-SoC Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson
2012	Misc	`conf`	Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. FCCM Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski
2012	A	`conf`	Impact of FPGA architecture on resource sharing in high-level synthesis. FPGA Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Brown, Tomasz S. Czajkowski
2012	A	`conf`	Leveraging reconfigurability to raise productivity in FPGA functional debug. DATE Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le
2012	J	`jnl`	Raising FPGA Logic Density Through Synthesis-Inspired Architecture. IEEE Trans. Very Large Scale Integr. Syst. Jason Helge Anderson, Qiang Wang, Chirag Ravishankar
2012	A	`conf`	The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson
2011	—	`conf`	An integer programming placement approach to FPGA clock power reduction. ASP-DAC Alireza Rakhshanfar, Jason Helge Anderson
2011	A	`conf`	Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. FPGA Jason Luu, Jason Helge Anderson, Jonathan Rose
2011	—	`conf`	Area-efficient FPGA logic elements: Architecture and synthesis. ASP-DAC Jason Helge Anderson, Qiang Wang
2011	A	`conf`	FPGA glitch power analysis and reduction. ISLPED Warren Wai-Kit Shum, Jason Helge Anderson
2011	B	`conf`	Latch-Based Performance Optimization for FPGAs. FPL Bill Teng, Jason Helge Anderson
2011	A	`conf`	LegUp: high-level synthesis for FPGA-based processor/accelerator systems. FPGA Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski
2011	—	`conf`	Low-cost hardware profiling of run-time and energy in FPGA embedded processors. ASAP Mark Aldham, Jason Helge Anderson, Stephen Brown, Andrew Canis
2011	B	`conf`	Reducing FPGA Router Run-Time through Algorithm and Architecture. FPL Marcel Gort, Jason Helge Anderson
2010	—	`conf`	A PUF design for secure FPGA-based embedded systems. ASP-DAC Jason Helge Anderson
2010	—	`conf`	Deterministic multi-core parallel routing for FPGAs. FPT Marcel Gort, Jason Helge Anderson
2010	A	`conf`	FPGA power reduction by guarded evaluation. FPGA Jason Helge Anderson, Chirag Ravishankar
2010	—	`conf`	Parallelizing FPGA placement using Transactional Memory. FPT Steven Birk, J. Gregory Steffan, Jason Helge Anderson
2009	B	`conf`	Clock gating architectures for FPGA power reduction. FPL Safeen Huda, Muntasir Mallick, Jason Helge Anderson
2009	A	`conf`	Clock power reduction for virtex-5 FPGAs. FPGA Qiang Wang, Subodh Gupta, Jason Helge Anderson
2009	A	`conf`	Emerging application domains: research challenges and opportunities for FPGAs. FPGA Jason Helge Anderson
2009	B	`conf`	Improving logic density through synthesis-inspired architecture. FPL Jason Helge Anderson, Qiang Wang
2009	J	`jnl`	Low-Power Programmable FPGA Routing Circuitry. IEEE Trans. Very Large Scale Integr. Syst. Jason Helge Anderson, Farid N. Najm
2009	J	`jnl`	Packing Techniques for Virtex-5 FPGAs. ACM Trans. Reconfigurable Technol. Syst. Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson
2008	A	`conf`	Architecture-specific packing for virtex-5 FPGAs. FPGA Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal
2007	—	`conf`	CAD Techniques for Power Optimization in Virtex-5 FPGAs. CICC Subodh Gupta, Jason Helge Anderson, Linda Farragher, Qiang Wang
2006	J	`jnl`	Active leakage power optimization for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Helge Anderson, Farid N. Najm
2004	—	`conf`	A novel low-power FPGA routing switch. CICC Jason Helge Anderson, Farid N. Najm
2004	A	`conf`	Active leakage power optimization for FPGAs. FPGA Jason Helge Anderson, Farid N. Najm, Tim Tuan
2004	—	`conf`	Interconnect capacitance estimation for FPGAs. ASP-DAC Jason Helge Anderson, Farid N. Najm
2004	A	`conf`	Low-power programmable routing circuitry for FPGAs. ICCAD Jason Helge Anderson, Farid N. Najm
2004	J	`jnl`	Power estimation techniques for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Jason Helge Anderson, Farid N. Najm
2004	B	`conf`	Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. FPL Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng
2003	—	`conf`	Switching activity analysis and pre-layout activity prediction for FPGAs. SLIP Jason Helge Anderson, Farid N. Najm
2002	—	`conf`	Power-aware technology mapping for LUT-based FPGAs. FPT Jason Helge Anderson, Farid N. Najm
2000	B	`conf`	A Placement Algorithm for FPGA Designs with Multiple I/O Standards. FPL Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman
1998	A	`conf`	An LPGA with Foldable PLA-style Logic Blocks. FPGA Jason Helge Anderson, Stephen Dean Brown
1998	A*	`conf`	Technology Mapping for Large Complex PLDs. DAC Jason Helge Anderson, Stephen Dean Brown