Jason Cong - RankMe

669 papers A* 85A 190B 10C 17Misc 40Journal 205Unranked 111

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	AI+HW 2035: Shaping the Next Decade. CoRR Deming Chen, Jason Cong, Azalia Mirhoseini, Christos Kozyrakis, Subhasish Mitra, Jinjun Xiong, Cliff Young, Anima Anandkumar, Michael L. Littman, Aron Kirschen, Sophia Shao, Serge Leef, Naresh R. Shanbhag, Dejan S. Milojicic, Michael Schulte, Gert Cauwenberghs, Jerry M. Chow, Tri Dao, Kailash Gopalakrishnan, Richard Ho, Hoshik Kim, Kunle Olukotun, David Z. Pan, Mark Ren, Dan Roth, Aarti Singh, Yizhou Sun, Yusu Wang, Yann LeCun, Ruchir Puri
2026	J	`jnl`	ARLArena: A Unified Framework for Stable Agentic Reinforcement Learning. CoRR Xiaoxuan Wang, Han Zhang, Haixin Wang, Yidan Shi, Ruoyan Li, Kaiqiao Han, Chenyi Tong, Haoran Deng, Renliang Sun, Alexander Taylor, Yanqiao Zhu, Jason Cong, Yizhou Sun, Wei Wang
2026	A	`conf`	AgRefactor: Refactoring for HLS Compatibility with a Self-Evolving Agentic Workflow. FPGA Yang Zou, Zijian Ding, Chi Wang, Yizhou Sun, Jason Cong
2026	—	`conf`	FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs. ASP-DAC Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama, Jason Cong, Callie Hao
2026	J	`jnl`	FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design. CoRR Jiahao Zhang, Zifan He, Nicholas Fraser, Michaela Blott, Yizhou Sun, Jason Cong
2026	J	`jnl`	Holistic Optimization Framework for FPGA Accelerators. ACM Trans. Design Autom. Electr. Syst. Stéphane Pouget, Michael Lo, Louis-Noël Pouchet, Jason Cong
2026	J	`jnl`	Report for NSF Workshop on AI for Electronic Design Automation. CoRR Deming Chen, Vijay Ganesh, Weikai Li, Yingyan Celine Lin, Yong Liu, Subhasish Mitra, David Z. Pan, Ruchir Puri, Jason Cong, Yizhou Sun
2026	J	`jnl`	Understand and Accelerate Memory Processing Pipeline for Disaggregated LLM Inference. CoRR Zifan He, Rui Ma, Yizhou Sun, Jason Cong
2025	A	`conf`	A Unified Framework for Automated Code Transformation and Pragma Insertion. FPGA Stéphane Pouget, Louis-Noël Pouchet, Jason Cong
2025	A*	`conf`	Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks. DAC Shuohao Ping, Wan-Hsuan Lin, Daniel Bochen Tan, Jason Cong
2025	A	`conf`	Automated Design Space Exploration in High-Level Physical Synthesis. ICCAD Linfeng Du, Jiawei Liang, Jason Lau, Yuze Chi, Yutong Xie, Chunyou Su, Afzal Ahmad, Zifan He, Jake Ke, Jinming Ge, Jason Cong, Wei Zhang, Licheng Guo
2025	J	`jnl`	Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. ACM Trans. Design Autom. Electr. Syst. Stéphane Pouget, Louis-Noël Pouchet, Jason Cong
2025	J	`jnl`	Can Asymmetric Tile Buffering Be Beneficial? CoRR Chengyue Wang, Wesley Pang, Xinrui Wu, Gregory Jun, Luis Romero, Endri Taka, Diana Marculescu, Tony Nowatzki, Pranathi Vasireddy, Joseph Melber, Deming Chen, Jason Cong
2025	—	`conf`	Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling. ASP-DAC Daniel Bochen Tan, Wan-Hsuan Lin, Jason Cong
2025	J	`jnl`	Demystifying FPGA Hard NoC Performance. CoRR Sihao Liu, Jake Ke, Tony Nowatzki, Jason Cong
2025	A*	`conf`	Dynamic-Width Speculative Beam Decoding for LLM Inference. AAAI Zongyue Qin, Zifan He, Neha Prakriya, Jason Cong, Yizhou Sun
2025	J	`jnl`	FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs. CoRR Stefan Abi-Karam, Rishov Sarkar, Suhail Basalama, Jason Cong, Callie Hao
2025	J	`jnl`	Fine Grain 3D Integration for Microarchitecture Design Through Cube Packing Exploration. CoRR Yongxiang Liu, Yuchun Ma, Eren Kurshan, Glenn Reinman, Jason Cong
2025	—	`conf`	HMT: Hierarchical Memory Transformer for Efficient Long Context Language Processing. NAACL (Long Papers) Zifan He, Yingqi Cao, Zongyue Qin, Neha Prakriya, Yizhou Sun, Jason Cong
2025	Misc	`conf`	HP-FFT: A General High-Performance FFT Generator Using High-Level Synthesis. FCCM Chengyue Wang, Jiahao Zhang, Yingquan Wu, Jason Cong
2025	A*	`conf`	Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis. AAAI Weikai Li, Ding Wang, Zijian Ding, Atefeh Sohrabizadeh, Zongyue Qin, Jason Cong, Yizhou Sun
2025	J	`jnl`	Holistic Optimization Framework for FPGA Accelerators. CoRR Stéphane Pouget, Michael Lo, Louis-Noël Pouchet, Jason Cong
2025	J	`jnl`	Iceberg: Enhancing HLS Modeling with Synthetic Data. CoRR Zijian Ding, Tung Nguyen, Weikai Li, Aditya Grover, Yizhou Sun, Jason Cong
2025	Misc	`conf`	InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs. FCCM Zifan He, Anderson Truong, Yingqi Cao, Jason Cong
2025	J	`jnl`	InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs. CoRR Zifan He, Anderson Truong, Yingqi Cao, Jason Cong
2025	A	`conf`	InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs. FPGA Zifan He, Hersh Gupta, Huifeng Ke, Jason Cong
2025	—	`conf`	Invited: Coping with Interconnects. ISPD Jason Cong
2025	J	`jnl`	LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning. CoRR Neha Prakriya, Zijian Ding, Yizhou Sun, Jason Cong
2025	J	`jnl`	LLM-DSE: Searching Accelerator Parameters with LLM Agents. CoRR Hanyu Wang, Xinrui Wu, Zijian Ding, Su Zheng, Chengyue Wang, Tony Nowatzki, Yizhou Sun, Jason Cong
2025	J	`jnl`	LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs. CoRR Zifan He, Shengyu Ye, Rui Ma, Yang Wang, Jason Cong
2025	—	`conf`	ML-QLS: Multilevel Quantum Layout Synthesis. ISPD Wan-Hsuan Lin, Jason Cong
2025	A*	`conf`	Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories. DAC Faaiq Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu
2025	J	`jnl`	Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories. CoRR Faaiq G. Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu
2025	Misc	`conf`	NoH: NoC Compilation in High-Level Synthesis. FCCM Huifeng Ke, Sihao Liu, Licheng Guo, Zifan He, Linghao Song, Suhail Basalama, Yuze Chi, Tony Nowatzki, Jason Cong
2025	A*	`conf`	Optimized Multi-Token Joint Decoding With Auxiliary Model for LLM Inference. ICLR Zongyue Qin, Ziniu Hu, Zifan He, Neha Prakriya, Jason Cong, Yizhou Sun
2025	A*	`conf`	Reconfigurable Stream Network Architecture. ISCA Chengyue Wang, Xiaofan Zhang, Jason Cong, James C. Hoe
2025	A*	`conf`	Reuse-Aware Compilation for Zoned Quantum Architectures Based on Neutral Atoms. HPCA Wan-Hsuan Lin, Daniel Bochen Tan, Jason Cong
2025	A	`conf`	Routing-Aware Placement for Zoned Neutral Atom-based Quantum Computing. ICCAD Yannick Stade, Wan-Hsuan Lin, Jason Cong, Robert Wille
2025	J	`jnl`	Routing-Aware Placement for Zoned Neutral Atom-based Quantum Computing. CoRR Yannick Stade, Wan-Hsuan Lin, Jason Cong, Robert Wille
2025	A	`conf`	SAT-Accel: A Modern SAT Solver on a FPGA. FPGA Michael Lo, Mau-Chung Frank Chang, Jason Cong
2025	A	`conf`	Stream-HLS: Towards Automatic Dataflow Acceleration. FPGA Suhail Basalama, Jason Cong
2025	J	`jnl`	Stream-HLS: Towards Automatic Dataflow Acceleration. CoRR Suhail Basalama, Jason Cong
2024	J	`jnl`	Accelerating Large Language Model Pretraining via LFR Pedagogy: Learn, Focus, and Review. CoRR Neha Prakriya, Jui-Nan Yen, Cho-Jui Hsieh, Jason Cong
2024	J	`jnl`	Addressing Architectural Obstacles for Overlay with Stream Network Abstraction. CoRR Chengyue Wang, Xiaofan Zhang, Jason Cong, James C. Hoe
2024	A*	`conf`	Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays. ISCA Hanrui Wang, Pengyu Liu, Daniel Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han
2024	A	`conf`	Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. FPGA Stéphane Pouget, Louis-Noël Pouchet, Jason Cong
2024	J	`jnl`	Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. CoRR Stéphane Pouget, Louis-Noël Pouchet, Jason Cong
2024	J	`jnl`	CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture. ACM Trans. Reconfigurable Technol. Syst. Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Shixin Ji, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Yiyu Shi, Deming Chen, Jason Cong, Peipei Zhou
2024	J	`jnl`	Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling. CoRR Daniel Bochen Tan, Wan-Hsuan Lin, Jason Cong
2024	J	`jnl`	Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors. Quantum Daniel Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong
2024	—	`conf`	Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis. MLCAD Zongyue Qin, Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Ziniu Hu, Yizhou Sun, Jason Cong
2024	J	`jnl`	Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis. CoRR Zongyue Qin, Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Ziniu Hu, Yizhou Sun, Jason Cong
2024	A	`conf`	Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization. DATE Daniel Bochen Tan, Shuohao Ping, Jason Cong
2024	J	`jnl`	Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization. CoRR Daniel Bochen Tan, Shuohao Ping, Jason Cong
2024	J	`jnl`	Dynamic-Width Speculative Beam Decoding for Efficient LLM Inference. CoRR Zongyue Qin, Zifan He, Neha Prakriya, Jason Cong, Yizhou Sun
2024	A	`conf`	Efficient Task Transfer for HLS DSE. ICCAD Zijian Ding, Atefeh Sohrabizadeh, Weikai Li, Zongyue Qin, Yizhou Sun, Jason Cong
2024	J	`jnl`	Efficient Task Transfer for HLS DSE. CoRR Zijian Ding, Atefeh Sohrabizadeh, Weikai Li, Zongyue Qin, Yizhou Sun, Jason Cong
2024	J	`jnl`	Enhancing High-Level Synthesis with Automated Pragma Insertion and Code Transformation Framework. CoRR Stéphane Pouget, Louis-Noël Pouchet, Jason Cong
2024	A	`conf`	GNN-Based Performance Prediction of Quantum Optimization of Maximum Independent Set. ICCAD Atefeh Sohrabizadeh, Wan-Hsuan Lin, Daniel Bochen Tan, Madelyn Cain, Sheng-Tao Wang, Mikhail D. Lukin, Jason Cong
2024	—	`conf`	Gossamer: Scaling Image Processing and Reconstruction to Whole Brains. BI (1) Karl Marrett, Keivan Moradi, Chris Sin Park, Ming Yan, Chris Choi, Muye Zhu, Masood Akram, Sumit Nanda, Qing Xue, Hyun-Seung Mun, Adriana E. Gutierrez, Mitchell Rudd, Brian Zingg, Gabrielle Magat, Kathleen Wijaya, Hongwei Dong, X. William Yang, Jason Cong
2024	J	`jnl`	HMT: Hierarchical Memory Transformer for Long Context Language Processing. CoRR Zifan He, Zongyue Qin, Neha Prakriya, Yizhou Sun, Jason Cong
2024	J	`jnl`	Harnessing GNNs for Robust Representation Learning in High-Level Synthesis. IEEE Trans. Circuits Syst. Artif. Intell. Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong
2024	J	`jnl`	Hierarchical Mixture of Experts: Generalizable Learning for High-Level Synthesis. CoRR Weikai Li, Ding Wang, Zijian Ding, Atefeh Sohrabizadeh, Zongyue Qin, Jason Cong, Yizhou Sun
2024	—	`conf`	High Throughput Training Label Generation from Whole Brain Images. BI (2) Karl Marrett, Keivan Moradi, Chris Sin Park, Ming Yan, Chris Choi, Muye Zhu, Masood Akram, Sumit Nanda, Qing Xue, Hyun-Seung Mun, Adriana E. Gutierrez, Mitchell Rudd, Brian Zingg, Gabrielle Magat, Kathleen Wijaya, Hongwei Dong, X. William Yang, Jason Cong
2024	—	`conf`	Learning to Compare Hardware Designs for High-Level Synthesis. MLCAD Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Haoxing Ren, Yizhou Sun, Jason Cong
2024	J	`jnl`	Learning to Compare Hardware Designs for High-Level Synthesis. CoRR Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Haoxing Ren, Yizhou Sun, Jason Cong
2024	A	`conf`	LevelST: Stream-based Accelerator for Sparse Triangular Solver. FPGA Zifan He, Linghao Song, Robert F. Lucas, Jason Cong
2024	J	`jnl`	ML-QLS: Multilevel Quantum Layout Synthesis. CoRR Wan-Hsuan Lin, Jason Cong
2024	J	`jnl`	Multi-Token Joint Speculative Decoding for Accelerating Large Language Model Inference. CoRR Zongyue Qin, Ziniu Hu, Zifan He, Neha Prakriya, Jason Cong, Yizhou Sun
2024	J	`jnl`	PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. Moazin Khatti, Xingyu Tian, Ahmad Sedigh Baroughi, Akhil Raj Baranwal, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang
2024	A*	`conf`	Q-Pilot: Field Programmable Qubit Array Compilation with Flying Ancillas. DAC Hanrui Wang, Daniel Bochen Tan, Pengyu Liu, Yilian Liu, Jiaqi Gu, Jason Cong, Song Han
2024	A	`conf`	Quantum State Preparation Circuit Optimization Exploiting Don't Cares. ICCAD Hanyu Wang, Daniel Bochen Tan, Jason Cong
2024	A	`conf`	Quantum State Preparation Using an Exact CNOT Synthesis Formulation. DATE Hanyu Wang, Jason Cong, Giovanni De Micheli
2024	J	`jnl`	Quantum State Preparation Using an Exact CNOT Synthesis Formulation. CoRR Hanyu Wang, Bochen Tan, Jason Cong, Giovanni De Micheli
2024	A	`conf`	RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. ICCAD Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo
2024	J	`jnl`	RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. CoRR Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo
2024	J	`jnl`	Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liqiang Lu, Zizhang Luo, Size Zheng, Jieming Yin, Jason Cong, Yun Liang, Jianwei Yin
2024	—	`conf`	Scheduling and Physical Design. ISPD Jason Cong
2024	A*	`conf`	SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering. DAC Tianqi Zhang, Neha Prakriya, Sumukh Pinge, Jason Cong, Tajana Rosing
2024	—	`conf`	TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. ASPLOS (3) Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong
2023	A*	`conf`	A Comprehensive Automated Exploration Framework for Systolic Array Designs. DAC Suhail Basalama, Jie Wang, Jason Cong
2023	J	`jnl`	A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware. CoRR Shichang Zhang, Atefeh Sohrabizadeh, Cheng Wan, Zijie Huang, Ziniu Hu, Yewen Wang, Yingyan Lin, Jason Cong, Yizhou Sun
2023	A	`conf`	CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture. FPGA Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou
2023	J	`jnl`	CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture. CoRR Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou
2023	—	`conf`	Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. ACM TUR-C Chen Zhang, Guangyu Sun, Zhenman Fang, Peipei Zhou, Jason Cong
2023	A	`conf`	Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. FPGA Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong
2023	J	`jnl`	Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors. CoRR Daniel Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong
2023	J	`jnl`	Democratizing Domain-Specific Computing. Commun. ACM Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2023	J	`jnl`	FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. Young Kyu Choi, Carlos Santillana, Yujia Shen, Adnan Darwiche, Jason Cong
2023	J	`jnl`	FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications. IEEE Trans. Biomed. Circuits Syst. Zhe Chen, Garrett J. Blair, Chengdi Cao, Jim Zhou, Daniel Aharoni, Peyman Golshani, Hugh T. Blair, Jason Cong
2023	J	`jnl`	FPQA-C: A Compilation Framework for Field Programmable Qubit Array. CoRR Hanrui Wang, Pengyu Liu, Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han
2023	J	`jnl`	FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA. ACM Trans. Reconfigurable Technol. Syst. Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Licheng Guo, Jason Cong
2023	A	`conf`	HMLib: Efficient Data Transfer for HLS Using Host Memory. FPGA Michael Lo, Young-kyu Choi, Weikang Qiao, Mau-Chung Frank Chang, Jason Cong
2023	A*	`conf`	Lightning Talk: Scaling Up Quantum Compilation - Challenges and Opportunities. DAC Jason Cong
2023	J	`jnl`	Locality and Utilization in Placement Suboptimality. CoRR Jason Cong, Michalis Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie
2023	J	`jnl`	Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. Proc. IEEE Gert Cauwenberghs, Jason Cong, X. Sharon Hu, Siddharth Joshi, Subhasish Mitra, Wolfgang Porod, H.-S. Philip Wong
2023	—	`conf`	NeSSA: Near-Storage Data Selection for Accelerated Machine Learning Training. HotStorage Neha Prakriya, Yu Yang, Baharan Mirzasoleiman, Cho-Jui Hsieh, Jason Cong
2023	Misc	`conf`	PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. FCCM Moazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang
2023	J	`jnl`	Q-Pilot: Field Programmable Quantum Array Compilation with Flying Ancillas. CoRR Hanrui Wang, Bochen Tan, Pengyu Liu, Yilian Liu, Jiaqi Gu, Jason Cong, Song Han
2023	J	`jnl`	RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
2023	A	`conf`	Robust GNN-Based Representation Learning for HLS. ICCAD Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong
2023	A*	`conf`	Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition. DAC Zizhang Luo, Liqiang Lu, Size Zheng, Jieming Yin, Jason Cong, Jianwei Yin, Yun Liang
2023	A*	`conf`	Scalable Optimal Layout Synthesis for NISQ Quantum Processors. DAC Wan-Hsuan Lin, Jason Kimko, Bochen Tan, Nikolaj S. Bjørner, Jason Cong
2023	J	`jnl`	TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. CoRR Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong
2023	J	`jnl`	TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ACM Trans. Reconfigurable Technol. Syst. Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
2023	J	`jnl`	TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Young Kyu Choi, Yuze Chi, Jason Lau, Jason Cong
2023	J	`jnl`	TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs. IEEE Trans. Emerg. Top. Comput. Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong
2023	A*	`conf`	Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs. NeurIPS Yunsheng Bai, Atefeh Sohrabizadeh, Zongyue Qin, Ziniu Hu, Yizhou Sun, Jason Cong
2022	Misc	`conf`	A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA. FCCM Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2022	A	`conf`	Accelerating SSSP for Power-Law Graphs. FPGA Yuze Chi, Licheng Guo, Jason Cong
2022	J	`jnl`	AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators. ACM Trans. Design Autom. Electr. Syst. Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong
2022	A	`conf`	Automated Accelerator Optimization Aided by Graph Neural Networks. FPGA Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong
2022	A*	`conf`	Automated accelerator optimization aided by graph neural networks. DAC Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong
2022	J	`jnl`	Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. CoRR Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong
2022	J	`jnl`	Democratizing Domain-Specific Computing. CoRR Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2022	J	`jnl`	Domain-Specific Quantum Architecture Optimization. CoRR Wan-Hsuan Lin, Bochen Tan, Murphy Yuezhen Niu, Jason Kimko, Jason Cong
2022	J	`jnl`	Domain-Specific Quantum Architecture Optimization. IEEE J. Emerg. Sel. Topics Circuits Syst. Wan-Hsuan Lin, Bochen Tan, Murphy Yuezhen Niu, Jason Kimko, Jason Cong
2022	C	`conf`	Efficient Kernels for Real-Time Position Decoding from In Vivo Calcium Images. ISCAS Zhe Chen, Jim Zhou, Garrett J. Blair, Hugh T. Blair, Jason Cong
2022	J	`jnl`	Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction. ACM Trans. Design Autom. Electr. Syst. Zhe Chen, Hugh T. Blair, Jason Cong
2022	J	`jnl`	FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Trans. Reconfigurable Technol. Syst. Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees A. Vissers, Zhiru Zhang
2022	A*	`conf`	Improving GNN-based accelerator design automation with meta learning. DAC Yunsheng Bai, Atefeh Sohrabizadeh, Yizhou Sun, Jason Cong
2022	—	`conf`	N-DISE: NDN-based data distribution for large-scale data-intensive science. ICN Yuanhao Wu, Faruk V. Mutlu, Yuezhou Liu, Edmund Yeh, Ran Liu, Catalin Iordache, Justas Balcas, Harvey B. Newman, Raimondas Sirvinskas, Michael Lo, Sichen Song, Jason Cong, Lixia Zhang, Sankalpa Timilsina, Susmit Shannigrahi, Chengyu Fan, Davide Pesavento, Junxiao Shi, Lotfi Benmohamed
2022	A*	`conf`	OverGen: Improving FPGA Usability through Domain-specific Overlay Generation. MICRO Sihao Liu, Jian Weng, Dylan Kupsh, Atefeh Sohrabizadeh, Zhengrong Wang, Licheng Guo, Jiuyang Liu, Maxim Zhulin, Rishabh Mani, Lucheng Zhang, Jason Cong, Tony Nowatzki
2022	Misc	`conf`	PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators. ICASSP Linghao Song, Yuze Chi, Jason Cong
2022	A	`conf`	Qubit Mapping for Reconfigurable Atom Arrays. ICCAD Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong
2022	A	`conf`	RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
2022	A	`conf`	SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation. FPGA Atefeh Sohrabizadeh, Yuze Chi, Jason Cong
2022	A*	`conf`	Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication. DAC Linghao Song, Yuze Chi, Licheng Guo, Jason Cong
2022	A	`conf`	Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. FPGA Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, Jason Cong
2022	—	`conf`	StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing. CICC Atefeh Sohrabizadeh, Yuze Chi, Jason Cong
2022	J	`jnl`	TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. CoRR Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
2022	Misc	`conf`	TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs. FCCM Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong
2022	J	`jnl`	TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs. CoRR Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong
2021	A	`conf`	AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. FPGA Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong
2021	A	`conf`	AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators. FPGA Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong
2021	A	`conf`	AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. FPGA Jie Wang, Licheng Guo, Jason Cong
2021	J	`jnl`	Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks. CoRR Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong
2021	Misc	`conf`	Extending High-Level Synthesis for Task-Parallel Programs. FCCM Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong
2021	A	`conf`	Extending High-Level Synthesis for Task-Parallel Programs. FPGA Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong
2021	Misc	`conf`	FANS: FPGA-Accelerated Near-Storage Sorting. FCCM Weikang Qiao, Jihun Oh, Licheng Guo, Mau-Chung Frank Chang, Jason Cong
2021	—	`conf`	Fast Calcium Trace Extraction for Large-Field-of-View Miniscope. BioCAS Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong
2021	A	`conf`	From Parallelization to Customization - Challenges and Opportunities. IPDPS Jason Cong
2021	A	`conf`	HBM Connect: High-Performance HLS Interconnect for FPGA HBM. FPGA Young-kyu Choi, Yuze Chi, Weikang Qiao, Nikola Samardzic, Jason Cong
2021	—	`conf`	Live Demonstration: Real-Time Calcium Trace Extraction from Large-Field-of-View Miniscope. BioCAS Zhe Chen, Garrett J. Blair, Changliang Guo, Daniel Aharoni, Hugh T. Blair, Jason Cong
2021	A	`conf`	MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators. FPGA Peipei Zhou, Jiayi Sheng, Cody Hao Yu, Peng Wei, Jie Wang, Di Wu, Jason Cong
2021	A	`conf`	Optimal Qubit Mapping with Simultaneous Gate Absorption ICCAD Special Session Paper. ICCAD Bochen Tan, Jason Cong
2021	J	`jnl`	Optimal Qubit Mapping with Simultaneous Gate Absorption. CoRR Bochen Tan, Jason Cong
2021	J	`jnl`	Optimality Study of Existing Quantum Computing Layout Synthesis Tools. IEEE Trans. Computers Bochen Tan, Jason Cong
2021	J	`jnl`	Pyxis: An Open-Source Performance Dataset of Sparse Accelerators. CoRR Linghao Song, Yuze Chi, Jason Cong
2021	J	`jnl`	SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation. CoRR Atefeh Sohrabizadeh, Yuze Chi, Jason Cong
2021	B	`conf`	Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. FMCAD Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra
2021	J	`jnl`	Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. CoRR Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra
2021	J	`jnl`	Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned. CoRR Jie Wang, Jason Cong
2021	J	`jnl`	Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication. CoRR Linghao Song, Yuze Chi, Licheng Guo, Jason Cong
2021	J	`jnl`	Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. CoRR Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, Jason Cong
2021	A*	`conf`	TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. ISCA Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang
2021	J	`jnl`	TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. CoRR Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang
2020	J	`jnl`	2019 DAC Roundtable. IEEE Des. Test Giovanni De Micheli, Antun Domic, Massimiliano Di Ventra, Martin Roettler, Jason Cong
2020	A*	`conf`	A-QED Verification of Hardware Accelerators. DAC Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, Subhasish Mitra
2020	Misc	`conf`	Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. FCCM Michael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang, Jason Cong
2020	A*	`conf`	Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. DAC Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
2020	A	`conf`	Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. FPGA Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
2020	J	`jnl`	AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators. CoRR Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong
2020	A	`conf`	BLINK: bit-sparse LSTM inference kernel enabling efficient calcium trace extraction for neurofeedback devices. ISLPED Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong
2020	A*	`conf`	Bonsai: High-Performance Adaptive Merge Tree Sorting. ISCA Nikola Samardzic, Weikang Qiao, Vaibhav Aggarwal, Mau-Chung Frank Chang, Jason Cong
2020	A	`conf`	CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real Time. FPGA Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong
2020	J	`jnl`	Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. IEEE Trans. Computers Yijin Guan, Guangyu Sun, Zhihang Yuan, Xingchen Li, Ningyi Xu, Shu Chen, Jason Cong, Yuan Xie
2020	A	`conf`	End-to-End Optimization of Deep Learning Applications. FPGA Atefeh Sohrabizadeh, Jie Wang, Jason Cong
2020	A*	`conf`	Exploiting Computation Reuse for Stencil Accelerators. DAC Yuze Chi, Jason Cong
2020	J	`jnl`	Extending High-Level Synthesis for Task-Parallel Programs. CoRR Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong
2020	J	`jnl`	FLASH: Fast, Parallel, and Accurate Simulator for HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Young-kyu Choi, Yuze Chi, Jie Wang, Jason Cong
2020	A	`conf`	HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration. FPGA Jiajie Li, Yuze Chi, Jason Cong
2020	A*	`conf`	HeteroRefactor: refactoring for heterogeneous computing with FPGA. ICSE Jason Lau, Aishwarya Sivaraman, Qian Zhang, Muhammad Ali Gulzar, Jason Cong, Miryung Kim
2020	A	`conf`	Optimal Layout Synthesis for Quantum Computing. ICCAD Bochen Tan, Jason Cong
2020	J	`jnl`	Optimal Layout Synthesis for Quantum Computing. CoRR Bochen Tan, Jason Cong
2020	J	`jnl`	Optimality Study of Existing Quantum Computing Layout Synthesis Tools. CoRR Bochen Tan, Jason Cong
2020	J	`jnl`	SACNN: Self-Attention Convolutional Neural Network for Low-Dose CT Denoising With Self-Supervised Perceptual Loss Network. IEEE Trans. Medical Imaging Meng Li, William Hsu, Xiaodong Xie, Jason Cong, Wen Gao
2020	A	`conf`	SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey
2020	J	`jnl`	When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. CoRR Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, Jason Cong
2019	J	`jnl`	A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications. IEEE J. Solid State Circuits Yanghyo Rod Kim, Boyu Hu, Yuan Du, Wei-Han Cho, Rulin Huang, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang
2019	Misc	`conf`	An FPGA-Based BWT Accelerator for Bzip2 Data Compression. FCCM Weikang Qiao, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong
2019	A	`conf`	Analyzing and Modeling In-Storage Computing Workloads On EISC - An FPGA-Based System-Level Emulation Platform. ICCAD Zhenyuan Ruan, Tong He, Jason Cong
2019	J	`jnl`	Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Zhang, Guangyu Sun, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong
2019	J	`jnl`	Customizable Computing - From Single Chip to Datacenters. Proc. IEEE Jason Cong, Zhenman Fang, Muhuan Huang, Peng Wei, Di Wu, Cody Hao Yu
2019	A	`conf`	Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis. FPGA Jie Liu, Jason Cong
2019	C	`conf`	Frequency Improvement of Systolic Array-Based CNNs on FPGAs. ISCAS Jiaxi Zhang, Wentai Zhang, Guojie Luo, Xuechao Wei, Yun Liang, Jason Cong
2019	Misc	`conf`	Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU. FCCM Licheng Guo, Jason Lau, Zhenyuan Ruan, Peng Wei, Jason Cong
2019	A	`conf`	HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
2019	—	`conf`	INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive. USENIX ATC Zhenyuan Ruan, Tong He, Jason Cong
2019	J	`jnl`	In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms. ACM Trans. Reconfigurable Technol. Syst. Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, Peng Wei
2019	A	`conf`	LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization. FPGA Zhe Chen, Hugh T. Blair, Jason Cong
2019	A	`conf`	Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment. FPGA Xuechao Wei, Yun Liang, Peng Zhang, Cody Hao Yu, Jason Cong
2019	A*	`conf`	Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management. DAC Xuechao Wei, Yun Liang, Jason Cong
2019	J	`jnl`	RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses. IEEE Trans. Computers Shuo Li, Nong Xiao, Peng Wang, Guangyu Sun, Xiaoyang Wang, Yiran Chen, Hai Helen Li, Jason Cong, Tao Zhang
2019	A	`conf`	Rapid Cycle-Accurate Simulator for High-Level Synthesis. FPGA Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang
2019	—	`conf`	Understanding Performance Gains of Accelerator-Rich Architectures. ASAP Zhenman Fang, Farnoosh Javadi, Jason Cong, Glenn Reinman
2018	—	`conf`	A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications. ISSCC Yanghyo Kim, Boyu Hu, Yuan Du, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang
2018	A	`conf`	An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only). FPGA Yuze Chi, Peipei Zhou, Jason Cong
2018	J	`jnl`	AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture. CoRR Jason Cong, Peng Wei, Cody Hao Yu, Peng Zhang
2018	A*	`conf`	Automated accelerator generation and optimization with composable, parallel and pipeline architecture. DAC Jason Cong, Peng Wei, Cody Hao Yu, Peng Zhang
2018	Misc	`conf`	Automatic Interior I/O Elimination in Systolic Array Architecture. FCCM Jason Cong, Jie Wang
2018	J	`jnl`	Best-Effort FPGA Programming: A Few Steps Can Go a Long Way. CoRR Jason Cong, Zhenman Fang, Yuchen Hao, Peng Wei, Cody Hao Yu, Chen Zhang, Peipei Zhou
2018	A	`conf`	CLINK: Compact LSTM Inference Kernel for Energy Efficient Neurofeedback Devices. ISLPED Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong
2018	J	`jnl`	CPU-FPGA Coscheduling for Big Data Applications. IEEE Des. Test Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu
2018	—	`conf`	Computed Tomography Image Enhancement Using 3D Convolutional Neural Network. DLMIA/ML-CDS@MICCAI Meng Li, Shiwen Shen, Wen Gao, William Hsu, Jason Cong
2018	J	`jnl`	Computed Tomography Image Enhancement using 3D Convolutional Neural Network. CoRR Meng Li, Shiwen Shen, Wen Gao, William Hsu, Jason Cong
2018	B	`conf`	Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-memory Computing Framework. ISPASS Peipei Zhou, Zhenyuan Ruan, Zhenman Fang, Megan Shand, David Roazen, Jason Cong
2018	A	`conf`	FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only). FPGA Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong
2018	—	`conf`	From JVM to FPGA: Bridging Abstraction Hierarchy via Optimized Deep Pipelining. HotCloud Jason Cong, Peng Wei, Cody Hao Yu
2018	A	`conf`	HLS-based optimization and design space exploration for applications with variable loop bounds. ICCAD Young-kyu Choi, Jason Cong
2018	Misc	`conf`	High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms. FCCM Weikang Qiao, Jieqiong Du, Zhenman Fang, Michael Lo, Mau-Chung Frank Chang, Jason Cong
2018	A	`conf`	High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only). FPGA Weikang Qiao, Jieqiong Du, Zhenman Fang, Libo Wang, Michael Lo, Mau-Chung Frank Chang, Jason Cong
2018	A	`conf`	K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only). FPGA Jason Cong, Zhenman Fang, Yao Hu, Di Wu
2018	—	`ch.`	Large-Scale Global Placement. Handbook of Approximation Algorithms and Metaheuristics (2) Jason Cong, Joseph R. Shinnerl
2018	Misc	`conf`	Latte: Locality Aware Transformation for High-Level Synthesis. FCCM Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou
2018	A	`conf`	PolySA: polyhedral-based systolic array auto-compilation. ICCAD Jason Cong, Jie Wang
2018	A*	`conf`	RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases. HPCA Peng Wang, Shuo Li, Guangyu Sun, Xiaoyang Wang, Yiran Chen, Hai Li, Jason Cong, Nong Xiao, Tao Zhang
2018	J	`jnl`	Rapid Cycle-Accurate Simulator for High-Level Synthesis. CoRR Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang
2018	A*	`conf`	S2FA: an accelerator automation framework for heterogeneous computing in datacenters. DAC Cody Hao Yu, Peng Wei, Max Grossman, Peng Zhang, Vivek Sarkar, Jason Cong
2018	Misc	`conf`	SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing. FCCM Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu
2018	B	`conf`	SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing. FPL Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu
2018	A	`conf`	SODA: stencil with optimized dataflow architecture. ICCAD Yuze Chi, Jason Cong, Peng Wei, Peipei Zhou
2018	Misc	`conf`	ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA. FCCM Zhenyuan Ruan, Tong He, Bojie Li, Peipei Zhou, Jason Cong
2018	—	`book`	Smartphone-Based Indoor Map Construction - Principles and Applications Ruipeng Gao, Fan Ye, Guojie Luo, Jason Cong
2018	A	`conf`	TGPA: tile-grained pipeline architecture for low latency CNN inference. ICCAD Xuechao Wei, Yun Liang, Xiuhong Li, Cody Hao Yu, Peng Zhang, Jason Cong
2018	Misc	`conf`	Understanding Performance Differences of FPGAs and GPUs. FCCM Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, Shaochong Zhang
2018	A	`conf`	Understanding Performance Differences of FPGAs and GPUs: (Abtract Only). FPGA Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, Shaochong Zhang
2017	Misc	`conf`	A cache-based bandwidth optimized motion compensation architecture for video decoder. ICASSP Meng Li, Huizhu Jia, Xiaodong Xie, Jason Cong, Wen Gao
2017	—	`conf`	AIM: accelerating computational genomics through scalable and noninvasive accelerator-interposed memory. MEMSYS Jason Cong, Zhenman Fang, Michael Gill, Farnoosh Javadi, Glenn Reinman
2017	A*	`conf`	Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. DAC Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong
2017	A*	`conf`	Bandwidth Optimization Through On-Chip Memory Restructuring for HLS. DAC Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou
2017	A	`conf`	CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only). FPGA Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu
2017	—	`conf`	Characterization and acceleration for genomic sequencing and analysis. IISWC Jason Cong
2017	A	`conf`	Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms. IPDPS Jie Wang, Xinfeng Xie, Jason Cong
2017	Misc	`conf`	FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. FCCM Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong
2017	—	`conf`	FPGA-based accelerator for long short-term memory recurrent neural networks. ASP-DAC Yijin Guan, Zhihang Yuan, Guangyu Sun, Jason Cong
2017	A	`conf`	HLScope+, : Fast and accurate performance estimation for FPGA HLS. ICCAD Young-kyu Choi, Peng Zhang, Peng Li, Jason Cong
2017	Misc	`conf`	HLScope: High-Level Performance Debugging for FPGA Designs. FCCM Young Kyu Choi, Jason Cong
2017	A*	`conf`	Supporting Address Translation for Accelerator-Centric Architectures. HPCA Yuchen Hao, Zhenman Fang, Glenn Reinman, Jason Cong
2017	—	`conf`	Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems. ASP-DAC Xuechao Wei, Yun Liang, Tao Wang, Songwu Lu, Jason Cong
2017	—	`conf`	Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators. APPT Yijin Guan, Ningyi Xu, Chen Zhang, Zhihang Yuan, Jason Cong
2016	J	`jnl`	A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alberto A. Del Barrio, Jason Cong, Román Hermida
2016	A	`conf`	A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only). FPGA Jie Lei, Yu-Ting Chen, Yunsong Li, Jason Cong
2016	A*	`conf`	A quantitative analysis on microarchitectures of modern CPU-FPGA platforms. DAC Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, Peng Wei
2016	—	`conf`	A scalable communication-aware compilation flow for programmable accelerators. ASP-DAC Jason Cong, Hui Huang, Mohammad Ali Ghodrat
2016	A	`conf`	ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only). FPGA Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou
2016	J	`jnl`	ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures. CoRR Yu-Ting Chen, Jason Cong, Zhenman Fang, Bingjun Xiao, Peipei Zhou
2016	J	`jnl`	Acceleration of EM-Based 3D CT Reconstruction Using FPGA. IEEE Trans. Biomed. Circuits Syst. Young Kyu Choi, Jason Cong
2016	J	`jnl`	An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Peng Li, Bingjun Xiao, Peng Zhang
2016	A	`conf`	Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks. ICCAD Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong
2016	Misc	`conf`	Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. FCCM Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, André DeHon
2016	A	`conf`	Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster. ISLPED Chen Zhang, Di Wu, Jiayu Sun, Guangyu Sun, Guojie Luo, Jason Cong
2016	J	`jnl`	FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ying Chen, Tan Nguyen, Yao Chen, Swathi T. Gurumani, Yun Liang, Kyle Rupnow, Jason Cong, Wen-mei W. Hwu, Deming Chen
2016	—	`ch.`	FPGA Technology Mapping. Encyclopedia of Algorithms Jason Cong, Yuzheng Ding
2016	A*	`conf`	Invited - Heterogeneous datacenters: options and opportunities. DAC Jason Cong, Muhuan Huang, Di Wu, Cody Hao Yu
2016	J	`jnl`	Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. IET Cyper-Phys. Syst.: Theory & Appl. Deming Chen, Jason Cong, Swathi T. Gurumani, Wen-mei W. Hwu, Kyle Rupnow, Zhiru Zhang
2016	—	`conf`	Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale. SoCC Muhuan Huang, Di Wu, Cody Hao Yu, Zhenman Fang, Matteo Interlandi, Tyson Condie, Jason Cong
2016	J	`jnl`	Revisiting FPGA Acceleration of Molecular Dynamics Simulation with Dynamic Data Flow Behavior in High-Level Synthesis. CoRR Jason Cong, Zhenman Fang, Hassan Kianinejad, Peng Wei
2016	—	`conf`	Scaling Up Physical Design: Challenges and Opportunities. ISPD Guojie Luo, Wentai Zhang, Jiaxi Zhang, Jason Cong
2016	A	`conf`	Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper. ISLPED Jason Cong, Muhuan Huang, Peichen Pan, Di Wu, Peng Zhang
2016	—	`ch.`	Source-to-Source Optimization for HLS. FPGAs for Software Programmers Jason Cong, Muhuan Huang, Peichen Pan, Yuxin Wang, Peng Zhang
2016	J	`jnl`	State of the Journal. IEEE Trans. Computers Paolo Montuschi, Edward J. McCluskey, Samarjit Chakraborty, Jason Cong, Ramón M. Rodríguez-Dagnino, Fred Douglis, Lieven Eeckhout, Gernot Heiser, Sushil Jajodia, Ruby B. Lee, Dinesh Manocha, Tomás F. Pena, Isabelle Puaut, Hanan Samet, Donatella Sciuto
2016	Misc	`conf`	The SMEM Seeding Acceleration for DNA Sequence Alignment. FCCM Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo, Cody Hao Yu
2016	Misc	`conf`	When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. FCCM Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, Peng Wei
2016	—	`conf`	When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. HotCloud Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, Peng Wei
2015	—	`conf`	"High-level synthesis and beyond - From datacenters to IoTs". SoCC Jason Cong
2015	Misc	`conf`	A Novel High-Throughput Acceleration Engine for Read Alignment. FCCM Yu-Ting Chen, Jason Cong, Jie Lei, Peng Wei
2015	B	`conf`	ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures. ISPASS Yu-Ting Chen, Jason Cong, Bingjun Xiao
2015	J	`jnl`	An automated lung segmentation approach using bidirectional chain codes to improve nodule detection accuracy. Comput. Biol. Medicine Shiwen Shen, Alex A. T. Bui, Jason Cong, William Hsu
2015	Misc	`conf`	Atlas: Baidu's key-value storage system for cloud data. MSST Chunbo Lai, Song Jiang, Liqiong Yang, Shiding Lin, Guangyu Sun, Zhenyu Hou, Can Cui, Jason Cong
2015	A*	`conf`	CMOST: a system-level FPGA compilation framework. DAC Peng Zhang, Muhuan Huang, Bingjun Xiao, Hui Huang, Jason Cong
2015	—	`book`	Customizable Computing Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, Bingjun Xiao
2015	A	`conf`	Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only). FPGA Jie Wang, Jason Cong
2015	A	`conf`	FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only). FPGA Wentai Zhang, Li Shen, Thomas Page, Guojie Luo, Peng Li, Peter Maaß, Ming Jiang, Jason Cong
2015	A	`conf`	Growing a Healthy FPGA Ecosystem. FPGA John Lockwood, Michael Adler, Dan Mansur, Derek Chiou, Mike Strickland, Jason Cong, Steve Teig
2015	C	`conf`	High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis. ICCE Meng Li, Peng Zhang, Chuang Zhu, Huizhu Jia, Xiaodong Xie, Jason Cong, Wen Gao
2015	A	`conf`	Impact of Loop Transformations on Software Reliability. ICCAD Jason Cong, Cody Hao Yu
2015	—	`conf`	InterFS: An Interplanted Distributed File System to Improve Storage Utilization. APSys Peng Wang, Le Cao, Chunbo Lai, Leqi Zou, Guangyu Sun, Jason Cong
2015	A	`conf`	Interconnect synthesis of heterogeneous accelerators in a shared memory architecture. ISLPED Yu-Ting Chen, Jason Cong
2015	A*	`conf`	On-chip interconnection network for accelerator-rich architectures. DAC Jason Cong, Michael Gill, Yuchen Hao, Glenn Reinman, Bo Yuan
2015	A	`conf`	Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. FPGA Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong
2015	A	`conf`	PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration. ICCAD Jason Cong, Zhenman Fang, Michael Gill, Glenn Reinman
2015	A	`conf`	Resource-Aware Throughput Optimization for High-Level Synthesis. FPGA Peng Li, Peng Zhang, Louis-Noël Pouchet, Jason Cong
2014	Misc	`conf`	A Fully Pipelined and Dynamically Composable Architecture of CGRA. FCCM Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao, Peipei Zhou
2014	B	`conf`	A scalable, high-performance customized priority queue. FPL Muhuan Huang, Kevin Lim, Jason Cong
2014	A*	`conf`	Accelerator-Rich Architectures: Opportunities and Progresses. DAC Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Karthik Gururaj, Glenn Reinman
2014	A	`conf`	Accelerator-rich architectures: from single-chip to datacenters. ISLPED Jason Cong
2014	A*	`conf`	An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers. DAC Jason Cong, Peng Li, Bingjun Xiao, Peng Zhang
2014	B	`conf`	An efficient and flexible host-FPGA PCIe communication library. FPL Jian Gong, Tao Wang, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu, Jason Cong
2014	A	`conf`	An efficient design and implementation of LSM-tree based key-value store on open-channel SSD. EuroSys Peng Wang, Guangyu Sun, Song Jiang, Jian Ouyang, Shiding Lin, Chen Zhang, Jason Cong
2014	J	`jnl`	Architecture Support for Domain-Specific Accelerator-Rich CMPs. ACM Trans. Embed. Comput. Syst. Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman
2014	—	`conf`	Automating customized computing. FPT Jason Cong
2014	J	`jnl`	Better-Than-Worst-Case Design: Progress and Opportunities. J. Comput. Sci. Technol. Jason Cong, Henry Duwe, Rakesh Kumar, Sen Li
2014	A	`conf`	Combining computation and communication optimizations in system synthesis for streaming applications. FPGA Jason Cong, Muhuan Huang, Peng Zhang
2014	A	`conf`	EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only). FPGA Jian Gong, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu, Jason Cong, Tao Wang
2014	Misc	`conf`	FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation. FCCM Peng Li, Thomas Page, Guojie Luo, Wentai Zhang, Pei Wang, Peng Zhang, Peter Maass, Ming Jiang, Jason Cong
2014	Misc	`conf`	FPGA Implementation of EM Algorithm for 3D CT Reconstruction. FCCM Young Kyu Choi, Jason Cong, Di Wu
2014	J	`jnl`	FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects. IEEE Trans. Very Large Scale Integr. Syst. Jason Cong, Bingjun Xiao
2014	—	`conf`	From design to design automation. ISPD Jason Cong
2014	J	`jnl`	GRT: A Reconfigurable SDR Platform with High Performance and Usability. SIGARCH Comput. Archit. News Tao Wang, Guangyu Sun, Jiahua Chen, Jian Gong, Haoyang Wu, Xiaoguang Li, Songwu Lu, Jason Cong
2014	C	`conf`	Minimizing Computation in Convolutional Neural Networks. ICANN Jason Cong, Bingjun Xiao
2014	J	`jnl`	System Light-Loading Technology for mHealth: Manifold-Learning-Based Medical Data Cleansing and Clinical Trials in WE-CARE Project. IEEE J. Biomed. Health Informatics Anpeng Huang, Wenyao Xu, Zhinan Li, Linzhen Xie, Majid Sarrafzadeh, Xiaoming Li, Jason Cong
2014	A	`conf`	Theory and algorithm for generalized memory partitioning in high-level synthesis. FPGA Yuxin Wang, Peng Li, Jason Cong
2014	A	`conf`	Transformations for throughput optimization in high-level synthesis (abstract only). FPGA Peng Li, Louis-Noël Pouchet, Deming Chen, Jason Cong
2013	C	`conf`	Accelerator-rich CMPs: From concept to real hardware. ICCD Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou
2013	J	`jnl`	An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guojie Luo, Yiyu Shi, Jason Cong
2013	A	`conf`	Architecture support for custom instructions with memory operations. FPGA Jason Cong, Karthik Gururaj
2013	A	`conf`	Are FPGAs suffering from the innovator's dilemna? FPGA Vaughn Betz, Jason Cong
2013	A	`conf`	Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only). FPGA Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong
2013	A	`conf`	Composable accelerator-rich microprocessor enhanced for adaptivity and longevity. ISLPED Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Hui Huang, Glenn Reinman
2013	A	`conf`	Defect recovery in nanodevice-based programmable interconnects (abstract only). FPGA Jason Cong, Bingjun Xiao
2013	A*	`conf`	Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance. DAC Jason Cong, Bingjun Xiao
2013	C	`conf`	Designing scratchpad memory architecture with emerging STT-RAM memory technologies. ISCAS Peng Wang, Guangyu Sun, Tao Wang, Yuan Xie, Jason Cong
2013	J	`jnl`	Efficient compilation of CUDA kernels for high-performance computing on FPGAs. ACM Trans. Embed. Comput. Syst. Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu
2013	A	`conf`	Efficient system-level mapping from streaming applications to FPGAs (abstract only). FPGA Jason Cong, Muhuan Huang, Peng Zhang
2013	A	`conf`	Energy-efficient computing using adaptive table lookup based on nonvolatile memories. ISLPED Jason Cong, Milos D. Ercegovac, Muhuan Huang, Sen Li, Bingjun Xiao
2013	Misc	`conf`	FPGA Simulation Engine for Customized Construction of Neural Microcircuit. FCCM Jason Cong, Hugh T. Blair, Di Wu
2013	A	`conf`	FPGA simulation engine for customized construction of neural microcircuits. ICCAD Hugh T. Blair, Jason Cong, Di Wu
2013	A	`conf`	Improving high level synthesis optimization opportunity through polyhedral transformations. FPGA Wei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, Jason Cong
2013	Misc	`conf`	Improving polyhedral code generation for high-level synthesis. CODES+ISSS Wei Zuo, Peng Li, Deming Chen, Louis-Noël Pouchet, Shunan Zhong, Jason Cong
2013	A*	`conf`	Memory partitioning for multidimensional arrays in high-level synthesis. DAC Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong
2013	A	`conf`	Optimization of interconnects between accelerators and shared memories in dark silicon. ICCAD Jason Cong, Bingjun Xiao
2013	—	`conf`	Optimizing routability in large-scale mixed-size placement. ASP-DAC Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao
2013	A	`conf`	Polyhedral-based data reuse optimization for configurable computing. FPGA Louis-Noël Pouchet, Peng Zhang, P. Sadayappan, Jason Cong
2013	J	`jnl`	Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects. ACM Trans. Archit. Code Optim. Chunhua Xiao, M.-C. Frank Chang, Jason Cong, Michael Gill, Zhangqin Huang, Chunyue Liu, Glenn Reinman, Hao Wu
2013	J	`jnl`	The survivability of design-specific spare placement in FPGA architectures with high defect rates. ACM Trans. Design Autom. Electr. Syst. Amit Agarwal, Jason Cong, Brian Tagiku
2013	A*	`conf`	Throughput-oriented kernel porting onto FPGAs. DAC Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu, Jason Cong, Yun Liang
2012	—	`conf`	A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration. CICC Hao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewnpu Jou, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang
2012	J	`jnl`	A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction. IEEE J. Emerg. Sel. Topics Circuits Syst. Jianwen Chen, Jason Cong, Luminita A. Vese, John D. Villasenor, Ming Yan, Yi Zou
2012	—	`conf`	A Study on the Impact of Compiler Optimizations on High-Level Synthesis. LCPC Jason Cong, Bin Liu, Raghu Prabhakar, Peng Zhang
2012	A*	`conf`	A metric for layout-friendly microarchitecture optimization in high-level synthesis. DAC Jason Cong, Bin Liu
2012	—	`conf`	An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. ISSCC Yanghyo Kim, Gyungsu Byun, Adrian Tang, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang
2012	—	`conf`	An integrated and automated memory optimization flow for FPGA behavioral synthesis. ASP-DAC Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
2012	J	`jnl`	Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface. IEEE J. Emerg. Sel. Topics Circuits Syst. Yanghyo Kim, Sai-Wang Tam, Gyungsu Byun, Hao Wu, Lan Nan, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang
2012	A*	`conf`	Architecture support for accelerator-rich CMPs. DAC Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman
2012	A	`conf`	BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs. ISLPED Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman
2012	A	`conf`	CHARM: a composable heterogeneous accelerator-rich microprocessor. ISLPED Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman
2012	A	`conf`	Combining module selection and replication for throughput-driven streaming programs. DATE Jason Cong, Muhuan Huang, Bin Liu, Peng Zhang, Yi Zou
2012	—	`conf`	Compilation and architecture support for customized vector instruction extension. ASP-DAC Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar, Glenn Reinman, Marco Vitanza
2012	A	`conf`	Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. DATE Yu-Ting Chen, Jason Cong, Hui Huang, Bin Liu, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman
2012	A	`conf`	Energy-efficient scheduling on heterogeneous multi-core architectures. ISLPED Jason Cong, Bo Yuan
2012	A	`conf`	FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only). FPGA Jason Cong, Bingjun Xiao
2012	A	`conf`	FPGA-accelerated 3D reconstruction using compressive sensing. FPGA Jianwen Chen, Jason Cong, Ming Yan, Yi Zou
2012	—	`conf`	Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. ISQED Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong
2012	B	`conf`	Mapping a data-flow programming model onto heterogeneous platforms. LCTES Alina Simion Sbîrlea, Yi Zou, Zoran Budimlic, Jason Cong, Vivek Sarkar
2012	A	`conf`	Memory partitioning and scheduling co-optimization in behavioral synthesis. ICCAD Peng Li, Yuxin Wang, Peng Zhang, Guojie Luo, Tao Wang, Jason Cong
2012	A*	`conf`	Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. DAC Jason Cong, Peng Zhang, Yi Zou
2012	—	`conf`	Platform characterization for Domain-Specific Computing. ASP-DAC Alex A. T. Bui, Kwang-Ting Cheng, Jason Cong, Luminita A. Vese, Yi-Chu Wang, Bo Yuan, Yi Zou
2012	A	`conf`	Static and dynamic co-optimizations for blocks mapping in hybrid caches. ISLPED Yu-Ting Chen, Jason Cong, Hui Huang, Chunyue Liu, Raghu Prabhakar, Glenn Reinman
2012	J	`jnl`	Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections. J. Electr. Comput. Eng. Jason Cong, Karthik Gururaj, Peng Zhang, Yi Zou
2012	—	`conf`	Towards layout-friendly high-level synthesis. ISPD Jason Cong, Bin Liu, Guojie Luo, Raghu Prabhakar
2012	—	`conf`	Transformation from ad hoc EDA to algorithmic EDA. ISPD Jason Cong
2012	J	`jnl`	Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system. ACM Trans. Archit. Code Optim. Kanit Therdsteerasukdi, Gyungsu Byun, Jason Cong, M. Frank Chang, Glenn Reinman
2012	J	`jnl`	Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System. IEEE J. Emerg. Sel. Topics Circuits Syst. Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang
2011	—	`conf`	3D recursive Gaussian IIR on GPU and FPGAs - A case for accelerating bandwidth-bounded applications. SASP Jason Cong, Muhuan Huang, Yi Zou
2011	A*	`conf`	A reuse-aware prefetching scheme for scratchpad memory. DAC Jason Cong, Hui Huang, Chunyue Liu, Yi Zou
2011	C	`conf`	A unified optimization framework for simultaneous gate sizing and placement under density constraints. ISCAS Jason Cong, John Lee, Guojie Luo
2011	A	`conf`	ATree-based topology synthesis for on-chip network. ICCAD Jason Cong, Yuhui Huang, Bo Yuan
2011	B	`conf`	Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms. FPL Jason Cong, Muhuan Huang, Yi Zou
2011	—	`conf`	Accelerating vision and navigation applications on a customizable platform. ASAP Jason Cong, Beayna Grigorian, Glenn Reinman, Marco Vitanza
2011	—	`conf`	An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling. ISSCC Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Hsieh-Hung Hsieh, P.-Y. Wu, Chewnpu Jou, Jason Cong, Glenn Reinman, Mau-Chung Frank Chang
2011	J	`jnl`	An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications. IEEE Trans. Very Large Scale Integr. Syst. Jeonghun Kim, Hanjun Choi, Sungyeal Yoon, Taesik Bang, Jongchan Park, Chaehyun Jung, Jason Cong
2011	A	`conf`	An energy-efficient adaptive hybrid cache. ISLPED Jason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman, Yi Zou
2011	A	`conf`	Assuring application-level correctness against soft errors. ICCAD Jason Cong, Karthik Gururaj
2011	J	`jnl`	Automatic memory partitioning and scheduling for throughput and power optimization. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Wei Jiang, Bin Liu, Yi Zou
2011	A	`conf`	Combined loop transformation and hierarchy allocation for data reuse optimization. ICCAD Jason Cong, Peng Zhang, Yi Zou
2011	J	`jnl`	Customizable Domain-Specific Computing. IEEE Des. Test Comput. Jason Cong, Glenn Reinman, Alex A. T. Bui, Vivek Sarkar
2011	—	`conf`	Domain-specific processor with 3D integration for medical image processing. ASAP Jason Cong, Karthik Gururaj, Muhuan Huang, Sen Li, Bingjun Xiao, Yi Zou
2011	—	`conf`	EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation. ISVC (1) Ming Yan, Jianwen Chen, Luminita A. Vese, John D. Villasenor, Alex A. T. Bui, Jason Cong
2011	—	`conf`	Era of customization and specialization. ASAP Jason Cong
2011	Misc	`conf`	HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support. CODES+ISSS Yu-Ting Chen, Jason Cong, Glenn Reinman
2011	J	`jnl`	High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang
2011	J	`jnl`	Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong
2011	Misc	`conf`	Multilevel Granularity Parallelism Synthesis on FPGAs. FCCM Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong
2011	J	`jnl`	Overview of Center for Domain-Specific Computing. J. Comput. Sci. Technol. Jason Cong
2011	J	`jnl`	Pattern-Mining for Behavioral Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Hui Huang, Wei Jiang
2011	—	`ch.`	RF-Interconnect for Future Network-On-Chip. Low Power Networks-on-Chip Sai-Wang Tam, Eran Socher, Mau-Chung Frank Chang, Jason Cong, Glenn D. Reinman
2011	A	`conf`	Resolving implicit barrier synchronizations in FPGA HLS (abstract only). FPGA Jason Cong, Yi Zou
2011	—	`conf`	Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong
2011	C	`conf`	The DIMM tree architecture: A high bandwidth and scalable memory system. ICCD Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, M. Frank Chang
2011	A*	`conf`	Thermal-aware cell and through-silicon-via co-placement for 3D ICs. DAC Jason Cong, Guojie Luo, Yiyu Shi
2011	—	`conf`	mrFPGA: A novel FPGA architecture with memristor-based reconfiguration. NANOARCH Jason Cong, Bingjun Xiao
2010	Misc	`conf`	A Comparative Study on the Architecture Templates for Dynamic Nested Loops. FCCM Jason Cong, Yi Zou
2010	A	`conf`	A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis. DATE Jason Cong, Hui Huang, Wei Jiang
2010	A*	`conf`	ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. DAC Jason Cong, Chunyue Liu, Glenn Reinman
2010	A	`conf`	Accelerating Monte Carlo based SSTA using FPGA. FPGA Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan, Yi Zou
2010	J	`jnl`	Advances and Challenges in 3D Physical Design. Inf. Media Technol. Jason Cong, Guojie Luo
2010	J	`jnl`	Advances and Challenges in 3D Physical Design. IPSJ Trans. Syst. LSI Des. Methodol. Jason Cong, Guojie Luo
2010	—	`conf`	An analytical placer for mixed-size 3D placement. ISPD Jason Cong, Guojie Luo
2010	J	`jnl`	Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Bin Liu, Rupak Majumdar, Zhiru Zhang
2010	A	`conf`	Bit-level optimization for high-level synthesis and FPGA-based acceleration. FPGA Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong
2010	A	`conf`	Coordinated resource optimization in behavioral synthesis. DATE Jason Cong, Bin Liu, Junjuan Xu
2010	J	`jnl`	Evaluating Statistical Power Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Puneet Gupta, John Lee
2010	J	`jnl`	LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. IEEE Trans. Very Large Scale Integr. Syst. Deming Chen, Jason Cong, Yiping Fan, Lu Wan
2010	A	`conf`	LUT-based FPGA technology mapping for reliability (abstract only). FPGA Jason Cong, Kirill Minkovich
2010	A*	`conf`	LUT-based FPGA technology mapping for reliability. DAC Jason Cong, Kirill Minkovich
2010	—	`conf`	Logic-on-logic 3D integration and placement. 3DIC Thorlindur Thorolfsson, Guojie Luo, Jason Cong, Paul D. Franzon
2010	J	`jnl`	NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Des. Test Comput. Robert K. Brayton, Jason Cong
2010	J	`jnl`	NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Des. Test Comput. Robert K. Brayton, Jason Cong
2010	J	`jnl`	Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng
2009	—	`conf`	A multilevel analytical placement for 3D ICs. ASP-DAC Jason Cong, Guojie Luo
2009	A	`conf`	A rigorous framework for convergent net weighting schemes in timing-driven placement. ICCAD Tony F. Chan, Jason Cong, Eric Radke
2009	A*	`conf`	A scalable micro wireless interconnect structure for CMPs. MobiCom Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng, Mishali Naik, Lixia Zhang, Jason Cong
2009	Misc	`conf`	A variation-tolerant scheduler for better than worst-case behavioral synthesis. CODES+ISSS Jason Cong, Albert Liu, Bin Liu
2009	A	`conf`	Automatic memory partitioning and scheduling for throughput and power optimization. ICCAD Jason Cong, Wei Jiang, Bin Liu, Yi Zou
2009	A	`conf`	Behavior-level observability don't-cares and application to low-power behavioral synthesis. ISLPED Jason Cong, Bin Liu, Zhiru Zhang
2009	B	`conf`	Customizable domain-specific computing. FPL Jason Cong
2009	A	`conf`	Energy efficient multiprocessor task scheduling under input-dependent variation. DATE Jason Cong, Karthik Gururaj
2009	Misc	`conf`	Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. FCCM Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou
2009	—	`conf`	FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. SASP Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu
2009	J	`jnl`	FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation. ACM Trans. Reconfigurable Technol. Syst. Jason Cong, Yi Zou
2009	A*	`conf`	From milliwatts to megawatts: system level power challenge. DAC Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach
2009	A	`conf`	High-performance CUDA kernel execution on FPGAs. ICS Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu
2009	A*	`conf`	Moore's Law: another casualty of the financial meltdown? DAC Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork
2009	—	`conf`	Multiband RF-interconnect for reconfigurable network-on-chip communications. SLIP Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam
2009	—	`conf`	On the futility of statistical power optimization. ASP-DAC Jason Cong, Puneet Gupta, John Lee
2009	A	`conf`	Parallel multi-level analytical global placement on graphics processing units. ICCAD Jason Cong, Yi Zou
2009	A	`conf`	Revisiting bitwidth optimizations. FPGA Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou
2009	A	`conf`	Scheduling with soft constraints. ICCAD Jason Cong, Bin Liu, Zhiru Zhang
2009	J	`jnl`	Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Yiping Fan, Junjuan Xu
2009	J	`jnl`	Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. IEEE Trans. Very Large Scale Integr. Syst. Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang
2009	A	`conf`	Synthesis of reconfigurable high-performance multicore systems. FPGA Jason Cong, Karthik Gururaj, Guoling Han
2009	J	`jnl`	The Last Byte: The HLS tipping point. IEEE Des. Test Comput. Jason Cong, Wolfgang Rosenstiel
2008	J	`jnl`	A Robust Mixed-Size Legalization and Detailed Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Min Xie
2008	—	`conf`	A new generation of C-base synthesis tool and domain-specific computing. SoCC Jason Cong
2008	—	`conf`	Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ASP-DAC Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang
2008	A*	`conf`	CMP network-on-chip overlaid with multi-band RF-interconnect. HPCA M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam
2008	J	`jnl`	Editorial: Special issue on 3D integrated circuits and microarchitectures. ACM J. Emerg. Technol. Comput. Syst. Yuan Xie, Jason Cong, Paul D. Franzon
2008	—	`ch.`	Enhancing Placement with Multilevel Techniques. Handbook of Algorithms for Physical Design Automation Jason Cong, Joseph R. Shinnerl
2008	—	`ch.`	FPGA Technology Mapping. Encyclopedia of Algorithms Jason Cong, Yuzheng Ding
2008	A	`conf`	Fault tolerant placement and defect reconfiguration for nano-FPGAs. ICCAD Amit Agarwal, Jason Cong, Brian Tagiku
2008	J	`jnl`	Highly Efficient Gradient Computation for Density-Constrained Analytical Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Guojie Luo, Eric Radke
2008	—	`conf`	Highly efficient gradient computation for density-constrained analytical placement methods. ISPD Jason Cong, Guojie Luo
2008	J	`jnl`	Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. ACM J. Emerg. Technol. Comput. Syst. Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong
2008	—	`conf`	LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong
2008	A	`conf`	Lithographic aerial image simulation with FPGA-based hardwareacceleration. FPGA Jason Cong, Yi Zou
2008	A	`conf`	MC-Sim: an efficient simulation tool for MPSoC designs. ICCAD Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman
2008	A	`conf`	Mapping for better than worst-case delays in LUT-based FPGA designs. FPGA Kirill Minkovich, Jason Cong
2008	A	`conf`	Pattern-based behavior synthesis for FPGA resource reduction. FPGA Jason Cong, Wei Jiang
2008	A*	`conf`	Power reduction of CMP communication networks via RF-interconnects. MICRO M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam
2008	—	`conf`	RF interconnects for communications on-chip. ISPD M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman
2008	—	`conf`	Robust gate sizing via mean excess delay minimization. ISPD Jason Cong, John Lee, Lieven Vandenberghe
2008	—	`conf`	Scheduling with integer time budgeting for low-power optimization. ASP-DAC Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong
2008	A	`conf`	Simultaneous FU and Register Binding Based on Network Flow Method. DATE Jason Cong, Junjuan Xu
2007	J	`jnl`	Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Trans. Parallel Distributed Syst. Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski
2007	C	`conf`	Fine grain 3D integration for microarchitecture design through cube packing exploration. ICCD Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong
2007	—	`conf`	High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang
2007	A	`conf`	Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. FPGA Jason Cong, Kirill Minkovich
2007	—	`ch.`	Large-Scale Global Placement. Handbook of Approximation Algorithms and Metaheuristics Joseph R. Shinnerl, Jason Cong
2007	—	`ch.`	Locality and Utilization in Placement Suboptimality. Modern Circuit Placement Jason Cong, Michalis Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie
2007	—	`conf`	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou
2007	—	`book`	Modern Circuit Placement, Best Practices and Results Gi-Joon Nam, Jason Cong
2007	J	`jnl`	Optimality Study of Logic Synthesis for LUT-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Kirill Minkovich
2007	J	`jnl`	Routability-Driven Placement and White Space Allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden
2007	A	`conf`	Synthesis of an application-specific soft multiprocessor system. FPGA Jason Cong, Guoling Han, Wei Jiang
2007	—	`conf`	Thermal-Aware 3D IC Placement Via Transformation. ASP-DAC Jason Cong, Guojie Luo, Jie Wei, Yan Zhang
2006	—	`conf`	A robust detailed placement for mixed-size IC designs. ASP-DAC Jason Cong, Min Xie
2006	—	`conf`	An automated design flow for 3D microarchitecture evaluation. ASP-DAC Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang
2006	A*	`conf`	An efficient and versatile scheduling algorithm based on SDC formulation. DAC Jason Cong, Zhiru Zhang
2006	J	`jnl`	Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. IEEE Trans. Very Large Scale Integr. Syst. Jason Cong, Guoling Han, Zhiru Zhang
2006	A*	`conf`	Behavior and communication co-optimization for systems with sequential communication media. DAC Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
2006	J	`jnl`	FPGA Design Automation: A Survey. Found. Trends Electron. Des. Autom. Deming Chen, Jason Cong, Peichen Pan
2006	J	`jnl`	Fast floorplanning by look-ahead enabled recursive bipartitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Michail Romesis, Joseph R. Shinnerl
2006	A*	`conf`	Optimal simultaneous mapping and clustering for FPGA delay optimization. DAC Joey Y. Lin, Deming Chen, Jason Cong
2006	J	`jnl`	Optimal simultaneous module and multivoltage assignment for low power. ACM Trans. Design Autom. Electr. Syst. Deming Chen, Jason Cong, Junjuan Xu
2006	A	`conf`	Optimality study of logic synthesis for LUT-based FPGAs. FPGA Jason Cong, Kirill Minkovich
2006	A*	`conf`	Optimality study of resource binding with multi-Vdds. DAC Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu
2006	—	`conf`	Platform-Based Behavior-Level and System-Level Synthesis. SoCC Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
2006	A	`conf`	Platform-based resource binding using a distributed register-file microarchitecture. ICCAD Jason Cong, Yiping Fan, Wei Jiang
2006	J	`jnl`	Protecting Combinational Logic Synthesis Solutions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong
2006	J	`jnl`	Simultaneous placement with clustering and duplication. ACM Trans. Design Autom. Electr. Syst. Gang Chen, Jason Cong
2006	—	`conf`	mPL6: enhanced multilevel mixed-size placement. ISPD Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie
2005	A	`conf`	Architecture and compilation for data bandwidth improvement in configurable embedded processors. ICCAD Jason Cong, Guoling Han, Zhiru Zhang
2005	—	`conf`	Are we ready for system-level synthesis? ASP-DAC Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe
2005	—	`conf`	Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng
2005	—	`conf`	Fast floorplanning by look-ahead enabled recursive bipartitioning. ASP-DAC Jason Cong, Michail Romesis, Joseph R. Shinnerl
2005	A	`conf`	Instruction set extension with shadow registers for configurable processors. FPGA Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
2005	J	`jnl`	Large-scale circuit placement. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan
2005	—	`conf`	Lower-bound estimation for multi-bitwidth scheduling. ISCAS (1) Junjuan Xu, Jason Cong, Xu Cheng
2005	J	`jnl`	MARS-a multilevel full-chip gridless routing system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Jie Fang, Min Xie, Yan Zhang
2005	—	`conf`	Microarchitecture evaluation with floorplanning and interconnect pipelining. ASP-DAC Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
2005	—	`conf`	Multilevel generalized force-directed method for circuit placement. ISPD Tony F. Chan, Jason Cong, Kenton Sze
2005	—	`conf`	Optimal module and voltage assignment for low-power. ASP-DAC Deming Chen, Jason Cong, Junjuan Xu
2005	J	`jnl`	Power modeling and characteristics of field programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong
2005	A	`conf`	Robust mixed-size placement under tight white-space constraints. ICCAD Jason Cong, Michail Romesis, Joseph R. Shinnerl
2005	A	`conf`	Simultaneous timing-driven placement and duplication. FPGA Gang Chen, Jason Cong
2005	J	`jnl`	Technology mapping and architecture evalution for ACM Trans. Design Autom. Electr. Syst. Jason Cong, Hui Huang, Xin Yuan
2005	A	`conf`	Thermal via planning for 3-D ICs. ICCAD Jason Cong, Yan Zhang
2005	—	`conf`	Thermal-driven multilevel routing for 3-D ICs. ASP-DAC Jason Cong, Yan Zhang
2005	A	`conf`	Understanding the energy efficiency of SMT and CMP with multiclustering. ISLPED Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir
2005	—	`conf`	mPL6: a robust multilevel mixed-size placement engine. ISPD Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie
2004	A	`conf`	A thermal-driven floorplanning algorithm for 3D ICs. ICCAD Jason Cong, Jie Wei, Yan Zhang
2004	—	`conf`	An area-optimality study of floorplanning. ISPD Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl
2004	A	`conf`	Application-specific instruction generation for configurable processor architectures. FPGA Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang
2004	J	`jnl`	Architecture and synthesis for on-chip multicycle communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
2004	A*	`conf`	Architecture-level synthesis for automatic interconnect pipelining. DAC Jason Cong, Yiping Fan, Zhiru Zhang
2004	A	`conf`	DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. ICCAD Deming Chen, Jason Cong
2004	A	`conf`	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ISLPED Deming Chen, Jason Cong
2004	J	`jnl`	Edge separability-based circuit clustering with application to multilevel circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Sung Kyu Lim
2004	A	`conf`	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA Fei Li, Yan Lin, Lei He, Jason Cong
2004	A	`conf`	Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA Deming Chen, Jason Cong, Fei Li, Lei He
2004	J	`jnl`	Optimality and scalability study of existing placement algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin-Chih Chang, Jason Cong, Michail Romesis, Min Xie
2004	—	`conf`	Register binding and port assignment for multiplexer optimization. ASP-DAC Deming Chen, Jason Cong
2004	J	`jnl`	Retiming-based timing analysis with an application to mincut-based global placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Sung Kyu Lim
2004	A	`conf`	Routability-driven placement and white space allocation. ICCAD Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden
2004	B	`conf`	Simultaneous Timing Driven Clustering and Placement for FPGAs. FPL Gang Chen, Jason Cong
2004	A*	`conf`	What happened to ASIC?: Go (recon)figure? DAC Nitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar
2003	A	`conf`	An Enhanced Multilevel Algorithm for Circuit Placement. ICCAD Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze
2003	A	`conf`	Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. ICCAD Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
2003	—	`conf`	Architecture and synthesis for multi-cycle communication. ISPD Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
2003	Misc	`conf`	Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
2003	A	`conf`	Architecture evaluation for power-efficient FPGAs. FPGA Fei Li, Deming Chen, Lei He, Jason Cong
2003	A	`conf`	Gradual Relaxation Techniques with Applications to Behavioral Synthesis. ICCAD Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong
2003	A	`conf`	Large-Scale Circuit Placement: Gap and Promise. ICCAD Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan
2003	A	`conf`	Low-power high-level synthesis for FPGA architectures. ISLPED Deming Chen, Jason Cong, Yiping Fan
2003	A*	`conf`	Microarchitecture evaluation with physical planning. DAC Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis
2003	—	`conf`	Multi-level placement for large-scale mixed-size IC designs. ASP-DAC Chin-Chih Chang, Jason Cong, Xin Yuan
2003	J	`jnl`	Multilevel global placement with congestion control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan
2003	A*	`conf`	Multilevel global placement with retiming. DAC Jason Cong, Xin Yuan
2003	A	`conf`	Optimality and Stability Study of Timing-Driven Placement Algorithms. ICCAD Jason Cong, Michail Romesis, Min Xie
2003	—	`conf`	Optimality and scalability study of existing placement algorithms. ASP-DAC Chin-Chih Chang, Jason Cong, Min Xie
2003	—	`conf`	Optimality, scalability and stability study of partitioning and placement algorithms. ISPD Jason Cong, Michail Romesis, Min Xie
2003	J	`jnl`	Performance-driven mapping for CPLD architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
2002	A	`conf`	A new enhanced SPFD rewiring algorithm. ICCAD Jason Cong, Joey Y. Lin, Wangning Long
2002	A	`conf`	An enhanced multilevel routing system. ICCAD Jason Cong, Min Xie, Yan Zhang
2002	J	`jnl`	An interconnect energy model considering coupling effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taku Uchino, Jason Cong
2002	—	`conf`	Enhanced SPFD Rewiring on Improving Rewiring Ability. IWLS Jason Cong, Joey Y. Lin, Wangning Long
2002	—	`conf`	Global clustering-based performance-driven circuit partitioning. ISPD Jason Cong, Chang Wu
2002	—	`conf`	Physical hierarchy generation with routing congestion control. ISPD Chin-Chih Chang, Jason Cong, David Zhigang Pan
2002	A	`conf`	SPFD-based global rewiring. FPGA Jason Cong, Yizhou Lin, Wangning Long
2002	—	`conf`	Timing closure based on physical hierarchy. ISPD Jason Cong
2002	J	`jnl`	Wire width planning for interconnect performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, David Zhigang Pan
2001	A*	`conf`	An Interconnect Energy Model Considering Coupling Effects. DAC Taku Uchino, Jason Cong
2001	J	`jnl`	An interconnect-centric design flow for nanometer technologies. Proc. IEEE Jason Cong
2001	J	`jnl`	Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Yean-Yow Hwang
2001	J	`jnl`	Buffer block planning for interconnect planning and prediction. IEEE Trans. Very Large Scale Integr. Syst. Jason Cong, Tianming Kong, Z. D. Pan
2001	J	`jnl`	DUNE-a multilayer gridless routing system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Jie Fang, Kei-Yong Khoo
2001	—	`conf`	Improved crosstalk modeling for noise constrained interconnect optimization. ASP-DAC Jason Cong, David Zhigang Pan, Prasanna V. Srinivas
2001	J	`jnl`	Interconnect layout optimization under higher order RLC model forMCM designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Cheng-Kok Koh, Patrick H. Madden
2001	J	`jnl`	Interconnect performance estimation models for design planning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, David Zhigang Pan
2001	J	`jnl`	Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
2001	A	`conf`	Multilevel Approach to Full-Chip Gridless Routing. ICCAD Jason Cong, Jie Fang, Yan Zhang VI
2001	A*	`conf`	Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. DAC Jason Cong, Michail Romesis
2001	A	`conf`	Performance-driven mapping for CPLD architectures. FPGA Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang
2001	J	`jnl`	Pseudopin assignment with crosstalk noise control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin-Chih Chang, Jason Cong
2001	A	`conf`	Simultaneous logic decomposition with technology mapping in FPGA designs. FPGA Gang Chen, Jason Cong
2000	—	`conf`	DUNE: a multi-layer gridless routing system with wire planning. ISPD Jason Cong, Jie Fang, Kei-Yong Khoo
2000	A*	`conf`	Depth optimal incremental mapping for field programmable gate arrays. DAC Jason Cong, Hui Huang
2000	—	`conf`	Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. ASP-DAC Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu
2000	—	`conf`	Edge separability based circuit clustering with application to circuit partitioning. ASP-DAC Jason Cong, Sung Kyu Lim
2000	A	`conf`	Incremental CAD. ICCAD Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh
2000	—	`conf`	Incremental physical design. ISPD Jason Cong, Majid Sarrafzadeh
2000	—	`conf`	Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. ASP-DAC Jason Cong, Songjie Xu
2000	—	`conf`	Multi-way partitioning using bi-partition heuristics. ASP-DAC Maogang Wang, Sung Kyu Lim, Jason Cong, Majid Sarrafzadeh
2000	A	`conf`	Multilevel Optimization for Large-Scale Circuit Placement. ICCAD Tony F. Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl
2000	A*	`conf`	Performance driven multi-level and multiway partitioning with retiming. DAC Jason Cong, Sung Kyu Lim, Chang Wu
2000	—	`conf`	Performance driven multiway partitioning. ASP-DAC Jason Cong, Sung Kyu Lim
2000	J	`jnl`	Performance-driven technology mapping for heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Songjie Xu
2000	A	`conf`	Physical Planning with Retiming. ICCAD Jason Cong, Sung Kyu Lim
2000	—	`conf`	Pseudo pin assignment with crosstalk noise control. ISPD Chin-Chih Chang, Jason Cong
2000	A*	`conf`	Routing tree construction under fixed buffer locations. DAC Jason Cong, Xin Yuan
2000	J	`jnl`	Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Yean-Yow Hwang
2000	A	`conf`	Synthesis for FPGAs with embedded memory blocks. FPGA Jason Cong, Kenneth Yan
2000	A	`conf`	Technology mapping for k/m-macrocell based FPGAs. FPGA Jason Cong, Hui Huang, Xin Yuan
2000	J	`jnl`	Via design rule consideration in multilayer maze routing algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Jie Fang, Kei-Yong Khoo
1999	J	`jnl`	An efficient approach to multilayer layer assignment with anapplication to via minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin-Chih Chang, Jason Cong
1999	A	`conf`	An implicit connection graph maze routing algorithm for ECO routing. ICCAD Jason Cong, Jie Fang, Kei-Yong Khoo
1999	A	`conf`	Buffer block planning for interconnect-driven floorplanning. ICCAD Jason Cong, Tianming Kong, David Zhigang Pan
1999	A	`conf`	Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. FPGA Jason Cong, Chang Wu, Yuzheng Ding
1999	—	`conf`	Interconnect Delay Estimation Models for Synthesis and Design Planning. ASP-DAC Jason Cong, David Zhigang Pan
1999	A*	`conf`	Interconnect Estimation and Dlanning for Deep Submicron Designs. DAC Jason Cong, David Zhigang Pan
1999	J	`jnl`	Optimal FPGA mapping and retiming with efficient initial state computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Chang Wu
1999	A	`ed.`	Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999 ISLPED Farid N. Najm, Jason Cong, David T. Blaauw
1999	—	`conf`	Relaxed Simulated Tempering for VLSI Floorplan Designs. ASP-DAC Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong
1999	A*	`conf`	Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. DAC Jason Cong, Honching Li, Chang Wu
1999	A*	`conf`	Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. DAC Jason Cong, Yean-Yow Hwang, Songjie Xu
1999	J	`jnl`	Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Lei He
1999	—	`conf`	VIA design rule consideration in multi-layer maze routing algorithms. ISPD Jason Cong, Jie Fang, Kei-Yong Khoo
1998	J	`jnl`	An efficient algorithm for performance-optimal FPGA technology mapping with retiming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Chang Wu
1998	—	`conf`	An efficient technique for device and interconnect optimization in deep submicron designs. ISPD Jason Cong, Lei He
1998	A	`conf`	Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. FPGA Jason Cong, Yean-Yow Hwang
1998	J	`jnl`	Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
1998	A*	`conf`	Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. DAC Jason Cong, Songjie Xu
1998	A	`conf`	Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources. ICCAD Jason Cong, Songjie Xu
1998	J	`jnl`	Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Andrew B. Kahng, Kwok-Shing Leung
1998	A	`conf`	How will CAD handle billion-transistor systems? (panel). ICCAD Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne H. Wolf
1998	A	`conf`	Intellectual property protection by watermarking combinational logic synthesis solutions. ICCAD Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong
1998	A	`conf`	Multiway partitioning with pairwise movement. ICCAD Jason Cong, Sung Kyu Lim
1998	A*	`conf`	Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. DAC Jason Cong, Chang Wu
1998	A*	`conf`	Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. DAC Jason Cong, Patrick H. Madden
1998	A	`ed.`	Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998 FPGA Jason Cong, Sinan Kaptanoglu
1998	A	`conf`	Technology Mapping for FPGAs with Embedded Memory Blocks. FPGA Jason Cong, Songjie Xu
1997	A*	`conf`	An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. DAC Chin-Chih Chang, Jason Cong
1997	A*	`conf`	Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen
1997	—	`conf`	Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. ISPD Jason Cong, Andrew B. Kahng, Kwok-Shing Leung
1997	A*	`conf`	FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. DAC Jason Cong, Chang Wu
1997	A	`conf`	Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan
1997	A	`conf`	Interconnect design for deep submicron ICs. ICCAD Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo
1997	A	`conf`	Interconnect layout optimization under higher-order RLC model. ICCAD Jason Cong, Cheng-Kok Koh
1997	A	`conf`	Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. ICCAD Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu
1997	Misc	`conf`	On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. FCCM Jason Cong, John Peck
1997	A	`conf`	Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. FPGA Jason Cong, Yean-Yow Hwang
1997	—	`conf`	Performance driven global routing for standard cell design. ISPD Jason Cong, Patrick H. Madden
1997	J	`jnl`	Performance-driven routing with multiple sources. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Patrick H. Madden
1996	C	`conf`	An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. ICCD Jason Cong, Chang Wu
1996	A	`conf`	An efficient approach to simultaneous transistor and interconnect sizing. ICCAD Jason Cong, Lei He
1996	A	`conf`	Buffered Steiner tree construction with wire sizing for interconnect layout optimization. ICCAD Takumi Okamoto, Jason Cong
1996	J	`jnl`	Combinational logic synthesis for LUT based field programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Yuzheng Ding
1996	J	`jnl`	Multiway VLSI circuit partitioning based on dual net representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Wilburt Labio, Narayanan Shivakumar
1996	J	`jnl`	Optimal wiresizing for interconnects with multiple sources. ACM Trans. Design Autom. Electr. Syst. Jason Cong, Lei He
1996	J	`jnl`	Performance optimization of VLSI interconnect layout. Integr. Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden
1996	A	`conf`	RASP: A General Logic Synthesis System for SRAM-Based FPGAs. FPGA Jason Cong, John Peck, Yuzheng Ding
1996	A	`conf`	Simultaneous buffer and wire sizing for performance and power optimization. ISLPED Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
1996	A*	`conf`	Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. DAC Jason Cong, Yean-Yow Hwang
1995	J	`jnl`	An efficient multilayer MCM router based on four-via routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kei-Yong Khoo, Jason Cong
1995	A	`conf`	Bounded-skew clock and Steiner routing under Elmore delay. ICCAD Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
1995	—	`conf`	Exploitation signal flow and logic dependency in standard cell placement. ASP-DAC Jason Cong, Dongmin Xu
1995	C	`conf`	Minimum-Cost Bounded-Skew Clock Routing. ISCAS Jason Cong, Cheng-Kok Koh
1995	A	`conf`	On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. FPGA Jason Cong, Yuzheng Ding
1995	A	`conf`	Optimal wiresizing for interconnects with multiple sources. ICCAD Jason Cong, Lei He
1995	J	`jnl`	Optimal wiresizing under Elmore delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Kwok-Shing Leung
1995	C	`conf`	Performance Driven Routing with Mulitiple Sources. ISCAS Jason Cong, Patrick H. Madden
1995	A	`conf`	Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. FPGA Jason Cong, Yean-Yow Hwang
1995	J	`jnl`	The Supercomputer Supernet: A Scalable Distributed Terabit Network. J. High Speed Networks Leonard Kleinrock, Mario Gerla, Nicholas Bambos, Jason Cong, Eli Gafni, Larry Bergman, Joseph A. Bannister
1994	A*	`conf`	Acyclic Multi-Way Partitioning of Boolean Networks. DAC Jason Cong, Zheng Li, Rajive L. Bagrodia
1994	J	`jnl`	Channel Density Minimization by Pin Permutation. VLSI Design Yang Cai, D. F. Wong, Jason Cong
1994	J	`jnl`	FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Yuzheng Ding
1994	J	`jnl`	LUT-based FPGA technology mapping under arbitrary net-delay models. Comput. Graph. Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen
1994	A	`conf`	Multi-way VLSI circuit partitioning based on dual net representation. ICCAD Jason Cong, Wilburt Labio, Narayanan Shivakumar
1994	J	`jnl`	On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. Jason Cong, Yuzheng Ding
1994	J	`jnl`	On nominal delay minimization in LUT-based FPGA technology mapping. Integr. Jason Cong, Yuzheng Ding
1994	J	`jnl`	On the Minimum Density Interconnection Tree Problem. VLSI Design Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
1994	Misc	`conf`	Parallel logic level simulation of VLSI circuits. WSC Rajive L. Bagrodia, Zheng Li, Vikas Jha, Yuan Chen, Jason Cong
1994	A	`conf`	Simultaneous driver and wire sizing for performance and power optimization. ICCAD Jason Cong, Cheng-Kok Koh
1994	J	`jnl`	Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. Very Large Scale Integr. Syst. Jason Cong, Cheng-Kok Koh
1993	A*	`conf`	A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. DAC Jason Cong, M'Lissa Smith
1993	Misc	`conf`	A Provably Good Algorithm for VLSI Design Jason Cong, Moazzem Hossain, Naveed A. Sherwani
1993	C	`conf`	A Two-pole Circuit Model for VLSI High-speed Interconnection. ISCAS Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong
1993	J	`jnl`	A provably good multilayer topological planar routing algorithm in IC layout designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Moazzem Hossain, Naveed A. Sherwani
1993	A*	`conf`	An Efficient Multilayer MCM Router Based on Four-Via Routing. DAC Kei-Yong Khoo, Jason Cong
1993	A	`conf`	Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. ICCAD Jason Cong, Yuzheng Ding
1993	J	`jnl`	Matching-based methods for high-performance clock routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Andrew B. Kahng, Gabriel Robins
1993	C	`conf`	Minimum Density Interconneciton Trees. ISCAS Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
1993	A*	`conf`	On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. DAC Jason Cong, Yuzheng Ding
1993	A	`conf`	Optimal wiresizing under the distributed Elmore delay model. ICCAD Jason Cong, Kwok-Shing Leung
1993	A*	`conf`	Performance-Driven Interconnect Design Based on Distributed RC Delay Model. DAC Jason Cong, Kwok-Shing Leung, Dian Zhou
1993	J	`jnl`	Physical models and efficient algorithms for over-the-cell routing in standard cell design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Bryan Preas, C. L. Liu
1992	—	`conf`	A fast multilayer general area router for MCM designs. EURO-DAC Kei-Yong Khoo, Jason Cong
1992	J	`jnl`	A new algorithm for standard cell global routing. Integr. Jason Cong, Bryan Preas
1992	C	`conf`	An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen
1992	A	`conf`	An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. ICCAD Jason Cong, Yuzheng Ding
1992	J	`jnl`	DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Des. Test Comput. Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar
1992	—	`conf`	Maximal reduction of lookup-table based FPGAs. EURO-DAC Kuang-Chien Chen, Jason Cong
1992	A*	`conf`	Net Partitions Yield Better Module Partitions. DAC Jason Cong, Lars W. Hagen, Andrew B. Kahng
1992	J	`jnl`	Provably good performance-driven global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong
1991	C	`conf`	A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. ICCD Jason Cong, Kei-Yong Khoo
1991	J	`jnl`	A layout modification approach to via minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Khe-Sing The, Martin D. F. Wong, Jason Cong
1991	A*	`conf`	High-Performance Clock Routing Based on Recursive Geometric Aatching. DAC Andrew B. Kahng, Jason Cong, Gabriel Robins
1991	J	`jnl`	On the k-layer planar subset and topological via minimization problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, C. L. Liu
1991	C	`conf`	Performance-Driven Global Routing for Cell Based ICs. ICCD Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong
1991	J	`jnl`	Pin assignment with global routing for general cell designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong
1990	A*	`conf`	General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. DAC Jason Cong, Bryan Preas, C. L. Liu
1990	—	`conf`	On the k-layer planar subset and via minimization problems. EURO-DAC Jason Cong, C. L. Liu
1990	J	`jnl`	Over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, C. L. Liu
1989	A	`conf`	Constrained floorplan design for flexible blocks. ICCAD Sai-keung Dong, Jason Cong, C. L. Liu
1989	A	`conf`	Pin assignment with global routing. ICCAD Jason Cong
1989	A*	`conf`	VIA Minimization by Layout Modification. DAC Khe-Sing The, D. F. Wong, Jason Cong
1988	J	`jnl`	A new approach to three- or four-layer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Martin D. F. Wong, C. L. Liu
1988	A	`conf`	A new formulation of yield enhancement problems for reconfigurable chips. ICCAD Nany Hasan, Jason Cong, C. L. Liu