Jared Zerbe

19 papers B 1Journal 8Unranked 10
YearRankTypeTitle / Venue / Authors
2015 J jnl
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits
Reza Navid, E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
2014 — conf
A 40-Gb/s serial link transceiver in 28-nm CMOS technology.
VLSIC
E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
2014 — conf
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
VLSIC
Masum Hossain, E-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-Huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble
2014 J jnl
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.
IEEE J. Solid State Circuits
Masum Hossain, Farrukh Aquil, Pak Shing Chau, Brian Tsang, Phuong Le, Jason Wei, Teva Stone, Barry Daly, Chanh Tran, John C. Eble, Kurt Knorpp, Jared Zerbe
2012 — conf
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.
CICC
Dustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble
2012 — conf
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS.
CICC
Kambiz Kaviani, Masum Hossain, Meisam Honarvar Nazari, Fred Heaton, Jihong Ren, Jared Zerbe
2012 — conf
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.
CICC
Masum Hossain, Kambiz Kaviani, Barry Daly, Makarand Shirasgaonkar, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Brian Tsang, John C. Eble, Jared Zerbe
2011 J jnl
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques.
IEEE J. Solid State Circuits
Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi T. Kollipara
2011 J jnl
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jaeha Kim, E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang
2011 — conf
Power-efficient I/O design considerations for high-bandwidth applications.
CICC
John C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John M. Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen
2010 — conf
Equalizer design and performance trade-offs in ADC-based serial links.
CICC
Jaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe
2009 J jnl
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits
Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi
2008 J jnl
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.
IEEE J. Solid State Circuits
E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Hae-Chang Lee, Qi Lin, Kyung Suk Oh, Frank Lambrecht, Vladimir Stojanovic, Jared Zerbe, Chih-Kong Ken Yang
2007 — conf
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
ISSCC
Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe
2006 — conf
Improving CDR Performance via Estimation.
ISSCC
Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz
2005 — conf
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.
CICC
Carl W. Werner, C. Hoyer, Andrew Ho, Metha Jeeradit, Fred Chen, Bruno W. Garlepp, Bill Stonecypher, Simon Li, Akash Bansal, Amita Agarwal, Elad Alon, Vladimir Stojanovic, Jared Zerbe
2003 B conf
Transition-limiting codes for 4-PAM signaling in high speed serial links.
GLOBECOM
Anthony G. Bessios, William F. Stonecypher, Amita Agarwal, Jared Zerbe
1998 J jnl
A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation.
IEEE J. Solid State Circuits
Matthew M. Griffin, Jared Zerbe, Grace Tsang, Michael Ching, Clemenz L. Portmann
1994 J jnl
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM.
IEEE J. Solid State Circuits
Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark Johnson, Tom Ishikawa