Janusz Rajski - RankMe

302 papers A* 12A 95B 21C 7Misc 41Journal 91Unranked 35

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Nonlinear Stream Cipher for Encryption of Test Patterns in Streaming Scan Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2025	A	`conf`	Automated Selection of Optimal EDT Input Configuration. ITC Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2025	J	`jnl`	Hybrid Ring Generators for In-System Testing. J. Electron. Test. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2025	B	`conf`	Identification of Failing Flip-Flops with Triangular Test Response Compaction. ETS Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2025	J	`jnl`	On Near-Maximum-Length Galois Nonlinear Feedback Shift Registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2025	Misc	`conf`	Timing-Verification Test Generation Targeting Small Delay Defects. VTS Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski
2024	A	`conf`	Delay Monitoring Under Different PVT Corners for Test and Functional Operation. ITC Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2024	A	`conf`	Deterministic In-Fleet Scan Test for a Cloud Computing Platform. ITC Dan Trock, Subramanian Mahadevan, Nilanjan Mukherjee, Lee Harrison, Janusz Rajski, Jerzy Tyszer
2024	J	`jnl`	Generation of Two-Cycle Tests for Structurally Similar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2024	J	`jnl`	H IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2024	A	`conf`	Test Data Encryption with a New Stream Cipher. ITC Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2024	J	`jnl`	The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer
2024	J	`jnl`	VLSI Test and Trust Roundtable. IEEE Des. Test Ramesh Karri, Janusz Rajski, Rob Aitken, Subhasish Mitra, Mark Tehranipoor
2023	J	`jnl`	A Lightweight True Random Number Generator for Root of Trust Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2023	J	`jnl`	A New Static Compaction of Deterministic Test Sets. IEEE Trans. Very Large Scale Integr. Syst. Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
2023	B	`conf`	Hybrid Ring Generators for In-System Test Applications. ETS Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2023	J	`jnl`	X-Masking for Deterministic In-System Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
2022	Misc	`conf`	Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
2022	A	`conf`	DIST: Deterministic In-System Test with X-masking. ITC Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
2022	J	`jnl`	Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski
2022	Misc	`conf`	Fast Test Generation for Structurally Similar Circuits. VTS Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2022	A	`conf`	Hardware Root of Trust for SSN-basedDFT Ecosystems. ITC Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2022	J	`jnl`	LBIST for Automotive ICs With Enhanced Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
2022	A	`conf`	Test Generation for an Iterative Design Flow with RTL Changes. ITC Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski
2022	B	`conf`	X-Masking for In-System Deterministic Test. ETS Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
2021	J	`jnl`	Autonomous Scan Patterns for Laser Voltage Imaging. IEEE Trans. Emerg. Top. Comput. Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2021	B	`conf`	Convolutional Compaction-Based MRAM Fault Diagnosis. ETS Bartosz Grzelak, Martin Keim, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2021	J	`jnl`	Defect-Oriented Test: Effectiveness in High Volume Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Friedrich Hapke, Will Howell, Peter C. Maxwell, Edward Brazil, Srikanth Venkataraman, Rudrajit Dutta, Andreas Glowatz, Anja Fast, Janusz Rajski
2021	A	`conf`	On Reduction of Deterministic Test Pattern Sets. ITC Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
2021	J	`jnl`	Time and Area Optimized Testing of Automotive ICs. IEEE Trans. Very Large Scale Integr. Syst. Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2021	J	`jnl`	X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. IEEE Trans. Very Large Scale Integr. Syst. Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
2020	J	`jnl`	Deterministic Stellar BIST for Automotive ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
2020	Misc	`conf`	Effective Design of Layout-Friendly EDT Decompressor. VTS Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer
2020	B	`conf`	Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
2020	—	`conf`	Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
2020	J	`jnl`	Low Cost Hypercompression of Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
2020	A	`conf`	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
2020	J	`jnl`	Scan Integrity Tests for EDT Compression. IEEE Des. Test Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2020	A	`conf`	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. ITC Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant
2020	B	`conf`	Test Sequence-Optimized BIST for Automotive Applications. ETS Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
2020	A	`conf`	X-Tolerant Tunable Compactor for In-System Test. ITC Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak
2019	J	`jnl`	Logic BIST With Capture-Per-Clock Hybrid Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
2019	Misc	`conf`	On Cyclic Scan Integrity Tests for EDT-based Compression. VTS Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2019	A	`conf`	Test Time and Area Optimized BrST Scheme for Automotive ICs. ITC Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki
2018	A	`conf`	DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies. ITC Will Howell, Friedrich Hapke, Edward Brazil, Srikanth Venkataraman, R. Datta, Andreas Glowatz, Wilfried Redemund, J. Schmerberg, Anja Fast, Janusz Rajski
2018	A	`conf`	Deterministic Stellar BIST for In-System Automotive Test. ITC Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
2018	J	`jnl`	Hardware Protection via Logic Locking Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael Chen, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2018	A	`conf`	Hypercompression of Test Patterns. ITC Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
2018	A	`conf`	On New Class of Test Points and Their Applications. ITC Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2018	Misc	`conf`	Staggered ATPG with capture-per-cycle observation test points. VTS Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer
2017	J	`jnl`	Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada
2017	A	`conf`	Full-scan LBIST with capture-per-cycle hybrid test points. ITC Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
2017	B	`conf`	ROM fault diagnosis for O(n ETS Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2017	J	`jnl`	Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
2017	J	`jnl`	Trimodal Scan-Based Test Paradigm. IEEE Trans. Very Large Scale Integr. Syst. Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang
2016	Misc	`conf`	Digital Testing of ICs for Automotive Applications. VLSID Nilanjan Mukherjee, Janusz Rajski
2016	A	`conf`	Minimal area test points for deterministic patterns. ITC Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer
2016	J	`jnl`	On New Test Points for Compact Cell-Aware Tests. IEEE Des. Test Cesar Acero, Derek Feltham, Marek Patyra, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2016	—	`conf`	On Test Points Enhancing Hardware Security. ATS Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2016	A	`conf`	Test point insertion in hybrid test compression/LBIST architectures. ITC Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2016	B	`conf`	Transistor stuck-on fault detection tests for digital CMOS circuits. ETS Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
2015	A	`conf`	A deterministic BIST scheme based on EDT-compressed test patterns. ITC Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
2015	—	`conf`	Clock-domain-aware test for improving pattern compression. VLSI-DAT Kun-Han Tsai, Janusz Rajski
2015	A*	`conf`	Design for low test pattern counts. DAC Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada
2015	A	`conf`	Embedded deterministic test points for compact cell-aware tests. ITC Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2015	—	`conf`	Hybrid Hierarchical and Modular Tests for SoC Designs. NATW Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski
2015	Misc	`conf`	Innovative practices session 11C: Advanced scan methodologies [3 presentations]. VTS Janusz Rajski, Nilanjan Mukherjee
2015	J	`jnl`	Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2015	J	`jnl`	Low-Power Programmable PRPG With Test Compression Capabilities. IEEE Trans. Very Large Scale Integr. Syst. Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2015	—	`conf`	On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ATS Xijiang Lin, Wu-Tung Cheng, Janusz Rajski
2015	J	`jnl`	Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2015	—	`conf`	TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm. ATS Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang
2015	Misc	`conf`	Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSID Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
2014	J	`jnl`	Cell-Aware Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Friedrich Hapke, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, Marek Hustava, Martin Keim, Juergen Schloeffel, Anja Fast
2014	B	`conf`	Cell-aware experiences in a high-quality automotive test suite. ETS Friedrich Hapke, Ralf Arnold, Matthias Beck, M. Baby, S. Straehle, J. F. Goncalves, A. Panait, R. Behr, Gwenolé Maugard, A. Prashanthi, Juergen Schloeffel, Wilfried Redemund, Andreas Glowatz, Anja Fast, Janusz Rajski
2014	J	`jnl`	Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	—	`conf`	High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. ATS Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
2014	A	`conf`	Isometric test compression with low toggling activity. ITC Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2014	—	`conf`	Low Power Test Compression with Programmable Broadcast-Based Control. ATS Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2014	A*	`conf`	On Using Implied Values in EDT-based Test Compression. DAC Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	C	`conf`	Quality assurance in memory built-in self-test tools. DDECS Albert Au, Artur Pogiel, Janusz Rajski, Piotr Sydow, Jerzy Tyszer, Justyna Zawada
2014	Misc	`conf`	Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players? VTS Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda
2014	—	`conf`	Test Compression Improvement with EDT Channel Sharing in SoC Designs. NATW Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung
2014	B	`conf`	Using dynamic shift to reduce test data volume in high-compression designs. ETS Xijiang Lin, Mark Kassab, Janusz Rajski
2013	A	`conf`	EDT bandwidth management - Practical scenarios for large SoC designs. ITC Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
2013	C	`conf`	Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören
2013	A	`conf`	Fault diagnosis of TSV-based interconnects in 3-D stacked designs. ITC Janusz Rajski, Jerzy Tyszer
2013	B	`conf`	New test compression scheme based on low power BIST. ETS Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2013	J	`jnl`	On Deploying Scan Chains for Data Storage in Test Compression Environment. IEEE Des. Test Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2013	—	`conf`	On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. Asian Test Symposium Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Thomas Rinderknecht
2013	A	`conf`	On the generation of compact test sets. ITC Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Chen Wang
2013	J	`jnl`	Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2012	B	`conf`	Bandwidth-aware test compression logic for SoC designs. ETS Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski
2012	A	`conf`	Cell-aware Production test results from a 32-nm notebook processor. ITC Friedrich Hapke, Michael Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski
2012	J	`jnl`	EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2012	A	`conf`	Low power programmable PRPG with enhanced fault coverage gradient. ITC Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2012	A	`conf`	Low power test application with selective compaction in VLSI designs. ITC Dariusz Czysz, Janusz Rajski, Jerzy Tyszer
2012	—	`conf`	On Utilizing Test Cube Properties to Reduce Test Data Volume Further. Asian Test Symposium Xijiang Lin, Janusz Rajski
2012	Misc	`conf`	Test generator with preselected toggling for low power built-in self-test. VTS Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie
2011	J	`jnl`	BIST-Based Fault Diagnosis for Read-Only Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2011	A	`conf`	Cell-aware analysis for small-delay effects and production test results from different fault models. ITC Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers
2011	J	`jnl`	Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
2011	B	`conf`	Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. ETS Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2011	A	`conf`	EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2011	—	`conf`	Fault Diagnosis in Memory BIST Environment with Non-march Tests. Asian Test Symposium Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek
2011	J	`jnl`	Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs. J. Electron. Test. Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2011	—	`conf`	Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer
2011	—	`conf`	Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki
2011	A	`conf`	Low power compression utilizing clock-gating. ITC Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy
2011	—	`conf`	Power Aware Embedded Test. Asian Test Symposium Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer
2011	B	`conf`	Reduced ATE Interface for High Test Data Compression. ETS Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2011	J	`jnl`	Ring Generator: An Ultimate Linear Feedback Shift Register. Computer Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer
2010	—	`conf`	Adaptive Low Shift Power Test Pattern Generator for Logic BIST. Asian Test Symposium Xijiang Lin, Janusz Rajski
2010	Misc	`conf`	At-speed scan test with low switching activity. VTS Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab
2010	B	`conf`	Diagnosis of failing scan cells through orthogonal response compaction. ETS Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2010	A	`conf`	Dynamic channel allocation for higher EDT compression in SoC designs. ITC Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
2010	J	`jnl`	High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2010	A	`conf`	Low capture power at-speed test in EDT environment. ITC Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab
2010	A	`conf`	Low power compression of incompatible test cubes. ITC Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
2010	J	`jnl`	On Compaction Utilizing Inter and Intra-Correlation of Unknown States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2009	A	`conf`	A scalable method for the generation of small test sets. DATE Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz
2009	A	`conf`	Compression based on deterministic vector clustering of incompatible test cubes. ITC Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2009	Misc	`conf`	Defect Aware to Power Conscious Tests - The New DFT Landscape. VLSI Design Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2009	A	`conf`	Fault diagnosis for embedded read-only memories. ITC Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2009	Misc	`conf`	High-Speed On-Chip Event Counters for Embedded Systems. VLSI Design Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2009	Misc	`conf`	Highly X-Tolerant Selective Compaction of Test Responses. VTS Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2009	J	`jnl`	Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2009	—	`conf`	N-distinguishing Tests for Enhanced Defect Diagnosis. Asian Test Symposium Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz
2009	J	`jnl`	Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2009	B	`conf`	We Have Got Compression, What Next? ETS Janusz Rajski
2008	—	`conf`	ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. DFT Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz
2008	A	`conf`	High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. ITC Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2008	J	`jnl`	Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2008	A	`conf`	Low Power Scan Shift and Capture in the EDT Environment. ITC Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2008	J	`jnl`	Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2008	A	`conf`	Test Generation for Interconnect Opens. ITC Xijiang Lin, Janusz Rajski
2008	—	`conf`	Test Power Reduction by Blocking Scan Cell Outputs. ATS Xijiang Lin, Janusz Rajski
2008	—	`conf`	Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2008	J	`jnl`	X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2007	A	`ed.`	2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007 ITC Jill Sibert, Janusz Rajski
2007	B	`conf`	Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. ETS Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware
2007	J	`jnl`	Enhancing delay fault coverage through low-power segmented scan. IET Comput. Digit. Tech. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
2007	J	`jnl`	Fault Diagnosis With Convolutional Compactors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2007	J	`jnl`	Isolation of Failing Scan Cells through Convolutional Test Response Compaction. J. Electron. Test. Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer
2007	C	`conf`	Logic Diagnosis and Yield Learning. DDECS Janusz Rajski
2007	Misc	`conf`	Low Power Embedded Deterministic Test. VTS Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2007	Misc	`conf`	Low Shift and Capture Power Scan Tests. VLSI Design Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2007	A*	`conf`	New Test Data Decompressor for Low Power Applications. DAC Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2007	J	`jnl`	Scan-Based Tests with Low Switching Activity. IEEE Des. Test Comput. Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2007	Misc	`conf`	Silicon Evaluation of Static Alternative Fault Models. VTS Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware
2007	—	`conf`	Test Generation for Timing-Critical Transition Faults. ATS Xijiang Lin, Mark Kassab, Janusz Rajski
2007	A*	`conf`	Test Generation in the Presence of Timing Exceptions and Constraints. DAC Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
2007	J	`jnl`	X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai
2006	A	`conf`	A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. ITC Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware
2006	A*	`conf`	A test pattern ordering algorithm for diagnosis with truncated fail data. DAC Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006	J	`jnl`	Analysis and methodology for multiple-fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2006	—	`conf`	At-Speed Testing with Timing Exceptions and Constraints-Case Studies. ATS Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo
2006	B	`conf`	Convolutional Compactors with Variable Polynomials. ETS Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2006	—	`conf`	Delay Fault Diagnosis for Non-Robust Test. ISQED Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski
2006	A	`conf`	Diagnosis with Limited Failure Information. ITC Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen
2006	B	`conf`	Enhancing Delay Fault Coverage through Low Power Segmented Scan. ETS Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
2006	J	`jnl`	High Performance Dense Ring Generators. IEEE Trans. Computers Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2006	Misc	`conf`	Modular Compactor of Test Responses. VTS Wojciech Rajski, Janusz Rajski
2006	Misc	`conf`	New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. VLSI Design Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006	A	`conf`	Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
2006	Misc	`conf`	Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
2006	A*	`conf`	Test response compactor with programmable selector. DAC Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2006	Misc	`conf`	The Impacts of Untestable Defects on Transition Fault Testing. VTS Xijiang Lin, Janusz Rajski
2006	A	`conf`	Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2006	—	`conf`	Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo
2006	A	`conf`	X-Press Compactor for 1000x Reduction of Test Data. ITC Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2005	B	`conf`	A unified fault model and test generation procedure for interconnect opens and bridges. ETS Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
2005	A	`conf`	Compressed pattern diagnosis for scan chain failures. ITC Yu Huang, Wu-Tung Cheng, Janusz Rajski
2005	B	`conf`	Convolutional compaction-driven diagnosis of scan failures. ETS Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang
2005	A	`conf`	Defect Aware Test Patterns. DATE Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz
2005	J	`jnl`	Delay-fault diagnosis using timing information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2005	A	`conf`	Diagnosis with convolutional compactors in presence of unknown states. ITC Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2005	—	`conf`	Embedded Test Technology - Brief History, Current Status, and Future Directions. Asian Test Symposium Janusz Rajski
2005	J	`jnl`	Finite memory test response compactors for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
2005	Misc	`conf`	On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz
2005	—	`conf`	Propagation delay fault: a new fault model to test delay faults. ASP-DAC Xijiang Lin, Janusz Rajski
2005	Misc	`conf`	Synthesis of X-Tolerant Convolutional Compactors. VTS Janusz Rajski, Jerzy Tyszer
2005	A	`conf`	Test compression - real issues and matching solutions. ITC Janusz Rajski
2004	A	`conf`	Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ITC Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski
2004	—	`conf`	Compactor Independent Direct Diagnosis. Asian Test Symposium Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski
2004	—	`conf`	Delay Fault Diagnosis Using Timing Information. ISQED Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2004	C	`conf`	Diagnosis of Hold Time Defects. ICCD Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2004	Misc	`conf`	Embedded Test for Low Cost Manufacturing. VLSI Design Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht
2004	J	`jnl`	Embedded deterministic test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
2004	A	`conf`	Fault Diagnosis in Designs with Convolutional Compactors. ITC Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski
2004	A	`conf`	Nanometer Design: What are the Requirements for Manufacturing Test? DATE Janusz Rajski, Kan Thapar
2004	Misc	`conf`	Planar High Performance Ring Generators. VTS Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2004	A	`conf`	Realizing High Test Quality Goals with Smart Test Resource Usage. ITC Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski
2004	J	`jnl`	Ring generators - new devices for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2003	J	`jnl`	2D Test Sequence Generators. IEEE Des. Test Comput. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
2003	A	`conf`	An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
2003	A	`conf`	Convolutional Compaction of Test Responses. ITC Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
2003	J	`jnl`	Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Des. Test Comput. Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
2003	Misc	`conf`	High Speed Ring Generators and Compactors of Test Data. VTS Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2003	J	`jnl`	High-Frequency, At-Speed Scan Testing. IEEE Des. Test Comput. Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli
2003	A	`conf`	Impact of Multiple-Detect Test Patterns on Product Quality. ITC Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski
2003	A	`conf`	Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
2003	C	`conf`	Multiple Fault Diagnosis Using n-Detection Tests. ICCD Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2003	A	`conf`	On Compacting Test Response Data Containing Unknown Values. ICCAD Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer
2003	J	`jnl`	Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients. J. Electron. Test. Janusz Rajski, Jerzy Tyszer
2003	A	`conf`	Test Challenges of Nanometer Technology. ITC Janusz Rajski
2003	C	`conf`	Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. ICCD Janusz Rajski, Jerzy Tyszer
2002	A	`conf`	Conflict driven techniques for improving deterministic test pattern generation. ICCAD Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
2002	A	`conf`	Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
2002	A	`conf`	Finding a Common Fault Response for Diagnosis during Silicon Debug. DATE Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy
2002	—	`conf`	Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. ASP-DAC/VLSI Design Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski
2002	Misc	`conf`	Innovations in Test Automation. VTS J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski
2001	—	`conf`	DFT for High-Quality Low Cost Manufacturing Test. Asian Test Symposium Janusz Rajski
2001	Misc	`conf`	Enabling Embedded Memory Diagnosis via Test Response Compression. VTS John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare
2001	A	`conf`	On static test compaction and test pattern ordering for scan designs. ITC Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy
2001	A	`conf`	Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
2001	J	`jnl`	Testing Schemes for FIR Filter Structures. IEEE Trans. Computers Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2000	J	`jnl`	Automated synthesis of phase shifters for built-in self-testapplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
2000	J	`jnl`	Cellular automata-based test pattern generators with phase shifters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2000	A	`conf`	Improving the Proportion of At-Speed Tests in Scan BIST. ICCAD Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski
2000	Misc	`conf`	Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. VTS Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
2000	A*	`conf`	Self-test methodology for at-speed test of crosstalk in chip interconnects. DAC Xiaoliang Bai, Sujit Dey, Janusz Rajski
2000	J	`jnl`	Star test: the theory and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska
1999	Misc	`conf`	Built-In Self-Test for Systems on Silicon. VLSI Design Janusz Rajski, Jerzy Tyszer, Sanjay Patel
1999	Misc	`conf`	Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. VTS Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer
1999	J	`jnl`	Diagnosis of Scan Cells in BIST Environment. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1999	A	`conf`	Logic BIST for large industrial designs: real issues and case studies. ITC Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski
1999	A	`conf`	STAR-ATPG: a high speed test pattern generator for large scan designs. ITC Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska
1999	A	`conf`	Synthesis of pattern generators based on cellular automata with phase shifters. ITC Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
1999	J	`jnl`	Testing of telecommunications hardware [Guest Editorial]. IEEE Commun. Mag. Janusz Rajski, Jerzy Tyszer
1998	A*	`conf`	A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. DAC Aiman H. El-Maleh, Mark Kassab, Janusz Rajski
1998	A	`conf`	Automated synthesis of large phase shifters for built-in self-test. ITC Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
1998	Misc	`conf`	Design of Phase Shifters for BIST Applications. VTS Janusz Rajski, Jerzy Tyszer
1998	A	`conf`	Modular logic built-in self-test for IP cores. ITC Janusz Rajski, Jerzy Tyszer
1998	J	`jnl`	Test Data Decompression for Multiple Scan Designs with Boundary Scan. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer, Nadime Zacharia
1997	J	`jnl`	Arithmetic built-in self-test for DSP cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer
1997	J	`jnl`	Behavior and testability preservation under the retiming transformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
1997	J	`jnl`	Design of Testable Multipliers for Fixed-Width Data Paths. IEEE Trans. Computers Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1997	A	`conf`	Fault Diagnosis in Scan-Based BIST. ITC Janusz Rajski, Jerzy Tyszer
1997	A	`conf`	Parameterizable Testing Scheme for FIR Filters. ITC Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1997	A*	`conf`	STARBIST: Scan Autocorrelated Random Pattern Generation. DAC Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska
1997	A	`conf`	Scan-Encoded Test Pattern Generation for BIST. ITC Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
1997	Misc	`conf`	Systems On Silicon: Design and Test Challenges. VTS J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian
1996	J	`jnl`	A complexity analysis of sequential ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski
1996	Misc	`conf`	A self-driven test structure for pseudorandom testing of non-scan sequential circuits. VTS Fidel Muradali, Janusz Rajski
1996	J	`jnl`	Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. IEEE Trans. Computers Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
1996	A	`conf`	Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. ITC Nagesh Tamarapalli, Janusz Rajski
1996	Misc	`conf`	Hardware-Software Co-Design for Test: It's the Last Straw! VTS J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard
1996	—	`conf`	Multiplicative Window Generators of Pseudo-random Test Vectors. ED&TC Janusz Rajski, Jerzy Tyszer
1996	J	`jnl`	On Linear Dependencies in Subspaces of LFSR-Generated Sequences. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1996	A	`conf`	Two-Dimensional Test Data Decompressor for Multiple Scan Designs. ITC Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski
1995	Misc	`conf`	Arithmetic built-in self test for high-level synthesis. VTS Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer
1995	J	`jnl`	Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Trans. Computers Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois
1995	—	`conf`	Complexity of sequential ATPG. ED&TC Thomas E. Marchok, Aiman El-Maleh, Wojciech Maly, Janusz Rajski
1995	Misc	`conf`	Decompression of test data using variable-length seed LFSRs. VTS Nadime Zacharia, Janusz Rajski, Jerzy Tyszer
1995	J	`jnl`	Delay-fault testability preservation of the concurrent decomposition and factorization transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aiman H. El-Maleh, Janusz Rajski
1995	Misc	`conf`	Fault coverage analysis of RAM test algorithms. VTS Marc D. Riedel, Janusz Rajski
1995	A	`conf`	Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC Mark Kassab, Janusz Rajski, Jerzy Tyszer
1995	A*	`conf`	On Test Set Preservation of Retimed Circuits. DAC Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
1995	A	`conf`	On testable multipliers for fixed-width data path architectures. ICCAD Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1995	A*	`conf`	Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1995	J	`jnl`	Testability Implications of Performance-Driven Logic Synthesis. IEEE Des. Test Comput. Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly
1994	Misc	`conf`	Delay-fault testability preservation of the concurrent decomposition and factorization transformations. VTS Aiman El-Maleh, Janusz Rajski
1994	J	`jnl`	On necessary and nonconflicting assignments in algorithmic test pattern generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Henry Cox, Janusz Rajski
1994	A	`conf`	Test pattern generation based on arithmetic operations. ICCAD Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
1993	J	`jnl`	Accumulator-Based Compaction of Test Responses. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1993	J	`jnl`	Recursive Pseudoexhaustive Test Pattern Generation. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1993	J	`jnl`	Test responses compaction in accumulators with rotate carry adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer
1993	J	`jnl`	The dynamic reduction of fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fadi Maamari, Janusz Rajski
1992	J	`jnl`	BIST of PCB interconnects using boundary-scan architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski
1992	J	`jnl`	Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. IEEE Des. Test Comput. Ashish Pancholy, Janusz Rajski, Larry J. McNaughton
1992	A	`conf`	Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. ITC Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski
1992	Misc	`conf`	Recent advances in logic synthesis with testability. VTS Janusz Rajski, Jagadeesh Vasudevamurthy, Aiman El-Maleh
1992	J	`jnl`	The testability-preserving concurrent decomposition and factorization of Boolean expressions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jagadeesh Vasudevamurthy
1991	J	`jnl`	A fault-tolerant array processor designed for testability and self-reconfiguration. IEEE J. Solid State Circuits Ajai Jain, Babu Mandava, Janusz Rajski, Nicholas C. Rumin
1991	A	`conf`	Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. ITC Stephen Pateras, Janusz Rajski
1991	A*	`conf`	Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. DAC Stephen Pateras, Janusz Rajski
1991	J	`jnl`	On the diagnostic properties of linear feedback shift registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer
1990	A	`conf`	A Method for Concurrent Decomposition and Factorization of Boolean Expressions. ICCAD Jagadeesh Vasudevamurthy, Janusz Rajski
1990	J	`jnl`	A method of fault simulation based on stem regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fadi Maamari, Janusz Rajski
1990	A	`conf`	A method to calculate necessary assignments in algorithmic test pattern generation. ITC Janusz Rajski, Henry Cox
1990	A	`conf`	Empirical failure analysis and validation of fault models in CMOS VLSI. ITC Ashish Pancholy, Janusz Rajski, Larry J. McNaughton
1990	A	`conf`	On the Diagnostic Resolution of Signature Analysis. ICCAD Janusz Rajski, Jerzy Tyszer, Babak Salimi
1990	A	`conf`	Testability preserving transformations in multi-level logic synthesis. ITC Janusz Rajski, Jagadeesh Vasudevamurthy
1990	A	`conf`	The dynamic reduction of fault simulation. ITC Fadi Maamari, Janusz Rajski
1989	A	`conf`	Testing of Glue Logic Interconnects Using Boundary Scan Architecture. ITC Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie
1988	A	`conf`	A fault simulation method based on stem regions. ICCAD Fadi Maamari, Janusz Rajski
1988	J	`jnl`	A method of fault analysis for test generation and fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Henry Cox, Janusz Rajski
1988	—	`conf`	A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits. FTCS Fadi Maamari, Janusz Rajski
1988	C	`conf`	A self-reconfiguration scheme for fault-tolerant VLSI processor arrays. ICCD Stephen Pateras, Janusz Rajski
1988	A	`conf`	An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. ITC Markus Robinson, Janusz Rajski
1988	—	`conf`	GEMINI-a logic system for fault diagnosis based on set functions. FTCS Janusz Rajski
1988	A	`conf`	On Multiple Fault Coverage and Aliasing Probability Measures. ITC Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski
1988	A	`conf`	Parallel PLA fault simulation based on Boolean vector operations. ICCAD Eli Chiprout, Janusz Rajski, Markus Robinson
1988	A	`conf`	Stuck-Open and Transition Fault Testing in CMOS Complex Gates. ITC Henry Cox, Janusz Rajski
1988	A	`conf`	Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. ITC Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski
1987	J	`jnl`	Testing and Applications of Inverter-Free PLAs. IEEE Des. Test Janusz Rajski, Vinod K. Agarwal
1986	J	`jnl`	The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1985	J	`jnl`	Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1985	A	`conf`	Testing Properties and Applications of Inverter-Free PLA's. ITC Vinod K. Agarwal, Janusz Rajski
1984	—	`conf`	The detection of small size multiple faults by single fault test sets n programmable logic arrays. Fehlertolerierende Rechensysteme Janusz Rajski, Jerzy Tyszer
1980	J	`jnl`	The Effect of Choosing the Switches for Rearrangements in Switching Networks. IEEE Trans. Commun. Andrzej Jajszczyk, Janusz Rajski