Janakiraman Viraraghavan

15 papers A* 1C 2Misc 2Journal 9Unranked 1
YearRankTypeTitle / Venue / Authors
2025 A* conf
GLiTCH: GLiTCH induced Transitions for Secure Crypto-Hardware.
DAC
C. Rohin Menon, Jayanth Balasubramanian, E. Akshay Kumar, Annapurna Valiveti, Chester Rebeiro, Janakiraman Viraraghavan
2024 J jnl
Input-Conditioned Quantisation for ENOB Improvement in CIM ADC Columns Targeting Large-Length Partial Sums.
IEEE Trans. Circuits Syst. II Express Briefs
S. Ashwin Balagopal, Janakiraman Viraraghavan, Balaji Vijayakumar
2023 J jnl
Geometric Programming Approach to Glitch Minimization via Gate Sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Karthikeyan Muthamizh Vithagan, Vignesh Sundaresha, Janakiraman Viraraghavan
2023 J jnl
Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection.
IEEE Trans. Educ.
Alfred Festus Davidson, Janakiraman Viraraghavan
2021 C conf
An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter.
ISCAS
Balaji Vijayakumar, Janakiraman Viraraghavan
2020 C conf
Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study.
ISCAS
S. Ashwin Balagopal, Janakiraman Viraraghavan
2020 J jnl
Statistical compact model extraction for skew-normal distributions.
IET Circuits Devices Syst.
Koduru Revanth, Janakiraman Viraraghavan
2018 J jnl
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits
Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer
2016 — conf
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
VLSI Circuits
Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer
2016 J jnl
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.
IEEE J. Solid State Circuits
Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer
2012 J jnl
Statistical Compact Model Extraction: A Neural Network Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts
2010 J jnl
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan
2008 Misc conf
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.
VLSI Design
Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind
2008 J jnl
Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks.
J. Low Power Electron.
Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan
2008 Misc conf
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization.
VLSI Design
Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur