Janak Sharda

15 papers A* 1C 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration.
CoRR
Wei-Hsing Huang, Janak Sharda, Cheng-Jhih Shih, Yuyao Kong, Faaiq Waqar, Pin-Jun Chen, Yingyan Lin, Shimeng Yu
2025 — conf
Monolithic 3D Stackable DRAM Design with BEOL-Compatible Oxide Channel Access Transistor.
IMW
Po-Kai Hsu, Sungwon Cho, Janak Sharda, Hyeonwoo Park, Suman Datta, Shimeng Yu
2025 A* conf
Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving.
MICRO
Yue Pan, Zihan Xia, Po-Kai Hsu, Lanxiang Hu, Hyungyo Kim, Janak Sharda, Minxuan Zhou, Nam Sung Kim, Shimeng Yu, Tajana Rosing, Mingu Kang
2025 J jnl
Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving.
CoRR
Yue Pan, Zihan Xia, Po-Kai Hsu, Lanxiang Hu, Hyungyo Kim, Janak Sharda, Minxuan Zhou, Nam Sung Kim, Shimeng Yu, Tajana Rosing, Mingu Kang
2025 J jnl
System-Technology Co-Optimization Methodology for LLM Accelerators With Advanced Packaging.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Janak Sharda, Shimeng Yu
2024 — conf
Accelerator Design using 3D Stacked Capacitorless DRAM for Large Language Models.
AICAS
Janak Sharda, Po-Kai Hsu, Shimeng Yu
2024 — conf
Impact of In-Pixel Processing Circuit Non-idealities on Multi-object Tracking Accuracy for Autonomous Driving.
MWSCAS
Janak Sharda, Qiucheng Wu, Shiyu Chang, Shimeng Yu
2024 J jnl
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Chun Luo, Anni Lu, Janak Sharda, Moritz Scherer, Jorge Tomás Gómez, Syed Shakib Sarwar, Ziyun Li, Reid Frederick Pinkham, Barbara De Salvo, Shimeng Yu
2023 J jnl
Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute.
IEEE Trans. Circuits Syst. I Regul. Pap.
Janak Sharda, Wantong Li, Qiucheng Wu, Shiyu Chang, Shimeng Yu
2022 J jnl
On-chip learning of a domain-wall-synapse-crossbar-array-based convolutional neural network.
Neuromorph. Comput. Eng.
Varun Bhavin Desai, Divya Kaushik, Janak Sharda, Debanjan Bhowmik
2022 — conf
Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving.
AICAS
Wantong Li, Qiucheng Wu, Janak Sharda, Shiyu Chang, Shimeng Yu
2021 C conf
A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning.
ISCAS
Janak Sharda, Ritvik Sharma, Debanjan Bhowmik
2020 — conf
Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning.
ICONS
Janak Sharda, Nilabjo Dey, Ankesh Jain, Debanjan Bhowmik
2019 — conf
On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network.
BioCAS
Nilabjo Dey, Janak Sharda, Utkarsh Saxena, Divya Kaushik, Utkarsh Singh, Debanjan Bhowmik
2019 J jnl
On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network.
CoRR
Nilabjo Dey, Janak Sharda, Utkarsh Saxena, Divya Kaushik, Utkarsh Singh, Debanjan Bhowmik