Janak H. Patel

184 papers A* 28A 40B 2C 8Misc 30Journal 41Unranked 35

Year	Rank	Type	Title / Venue / Authors
2005	C	`conf`	Hardware Ef.cient LBISTWith Complementary Weights. ICCD Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
2004	—	`conf`	Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs. ISVLSI Mihir A. Shah, Janak H. Patel
2004	Misc	`conf`	Logic BIST Using Constrained Scan Cells. VTS Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel
2004	A	`conf`	Logic BIST with Scan Chain Segmentation. ITC Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
2004	J	`jnl`	Partial Scan Design Based on Circuit State Information and Functional Analysis. IEEE Trans. Computers Dong Xiang, Janak H. Patel
2004	—	`conf`	The evolution of dependable computing at the University of Illinois. IFIP Congress Topical Sessions Ravishankar K. Iyer, William H. Sanders, Janak H. Patel, Zbigniew Kalbarczyk
2004	Misc	`conf`	What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit? VTS Manish Sharma, Janak H. Patel
2003	Misc	`conf`	Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. VTS Janak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy
2003	Misc	`conf`	Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. VTS Manish Sharma, Janak H. Patel, Jeff Rearick
2002	A	`conf`	An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs. DATE Amit R. Pandey, Janak H. Patel
2002	A	`conf`	Finding a Small Set of Longest Testable Paths that Cover Every Gate. ITC Manish Sharma, Janak H. Patel
2002	Misc	`conf`	Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . VTS Amit R. Pandey, Janak H. Patel
2001	Misc	`conf`	A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification. VLSI Design Jian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel
2001	A	`conf`	A case study on the implementation of the Illinois Scan Architecture. ITC Frank F. Hsu, Kenneth M. Butler, Janak H. Patel
2001	J	`jnl`	Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Trans. Design Autom. Electr. Syst. Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty
2001	A	`conf`	Testing of critical paths for delay faults. ITC Manish Sharma, Janak H. Patel
2000	Misc	`conf`	Bounding Circuit Delay by Testing a Very Small Subset of Paths. VTS Manish Sharma, Janak H. Patel
2000	A	`conf`	Deterministic Test Pattern Generation Techniques for Sequential Circuits. ICCAD Ilker Hamzaoglu, Janak H. Patel
2000	J	`jnl`	Dynamic state traversal for sequential circuit test generation. ACM Trans. Design Autom. Electr. Syst. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
2000	A	`conf`	Enhanced delay defect coverage with path-segments. ITC Manish Sharma, Janak H. Patel
2000	J	`jnl`	Peak power estimation of VLSI circuits: new peak power measures. IEEE Trans. Very Large Scale Integr. Syst. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
2000	Misc	`conf`	Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. VTS Ilker Hamzaoglu, Janak H. Patel
2000	J	`jnl`	Test set compaction algorithms for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ilker Hamzaoglu, Janak H. Patel
1999	Misc	`conf`	A Test Generator for Segment Delay Faults. VLSI Design Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1999	Misc	`conf`	An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. VLSI Design Zbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer
1999	J	`jnl`	Efficient Techniques for Dynamic Test Sequence Compaction. IEEE Trans. Computers Elizabeth M. Rudnick, Janak H. Patel
1999	J	`jnl`	Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. IEEE Trans. Computers Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1999	J	`jnl`	New Techniques for Deterministic Test Pattern Generation. J. Electron. Test. Ilker Hamzaoglu, Janak H. Patel
1999	—	`conf`	Reducing Test Application Time for Full Scan Embedded Cores. FTCS Ilker Hamzaoglu, Janak H. Patel
1998	—	`conf`	A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. 25 Years ISCA: Retrospectives and Reprints Mark S. Papamarcos, Janak H. Patel
1998	J	`jnl`	Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1998	A	`conf`	Compact two-pattern test set generation for combinational and full scan circuits. ITC Ilker Hamzaoglu, Janak H. Patel
1998	Misc	`conf`	Diagnostic Simulation of Sequential Circuits Using Fault Sampling. VLSI Design Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel
1998	C	`conf`	Enhancing topological ATPG with high-level information and symbolic techniques. ICCD Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, Roberto Vietti
1998	J	`jnl`	High-Level Controllability and Observability Analysis for Test Synthesis. J. Electron. Test. Frank F. Hsu, Janak H. Patel
1998	A	`conf`	High-level variable selection for partial-scan implementation. ICCAD Frank F. Hsu, Janak H. Patel
1998	—	`conf`	Improving the Throughput of a Pipeline by Insertion of Delays. 25 Years ISCA: Retrospectives and Reprints Janak H. Patel, Edward S. Davidson
1998	Misc	`conf`	New Techniques for Deterministic Test Pattern Generation. VTS Ilker Hamzaoglu, Janak H. Patel
1998	Misc	`conf`	Partial Scan Selection Based on Dynamic Reachability and Observability Information. VLSI Design Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel
1998	—	`conf`	Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. 25 Years ISCA: Retrospectives and Reprints Janak H. Patel
1998	—	`conf`	Retrospective: Improving the Throughput of a Pipeline by Insertion of Delays. 25 Years ISCA: Retrospectives and Reprints Janak H. Patel
1998	A	`conf`	Stuck-at fault: a fault model for the next millennium. ITC Janak H. Patel
1998	A	`conf`	Test set compaction algorithms for combinational circuits. ICCAD Ilker Hamzaoglu, Janak H. Patel
1997	J	`jnl`	A genetic algorithm framework for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
1997	J	`jnl`	Algorithms to compute bridging fault coverage of ACM Trans. Design Autom. Electr. Syst. Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel
1997	—	`conf`	Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. Workshop on Parallel and Distributed Simulation Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel
1997	A	`conf`	BART: A Bridging Fault Test Generation for Sequential Circuits. ITC James P. Cusey, Janak H. Patel
1997	J	`jnl`	Design for Testability Using State Distances. J. Electron. Test. Frank F. Hsu, Janak H. Patel
1997	Misc	`conf`	Diagnostic Test Pattern Generation for Sequential Circuits. VTS Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs
1997	Misc	`conf`	Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. VLSI Design Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel
1997	A	`conf`	Effects of delay models on peak power estimation of VLSI sequential circuits. ICCAD Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1997	Misc	`conf`	Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. VTS Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1997	A	`conf`	Fast identification of untestable delay faults using implications. ICCAD Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1997	J	`jnl`	Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
1997	A	`conf`	K2: an estimator for peak sustainable power of VLSI circuits. ISLPED Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1997	Misc	`conf`	Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. VLSI Design Elizabeth M. Rudnick, Janak H. Patel
1997	Misc	`conf`	Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. VLSI Design Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee
1997	—	`conf`	Partial Scan beyond Cycle Cutting. FTCS Gurjeet S. Saund, Michael S. Hsiao, Janak H. Patel
1997	A	`conf`	Putting the Squeeze on Test Sequences. ITC Elizabeth M. Rudnick, Janak H. Patel
1997	Misc	`conf`	SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. VTS Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee
1997	—	`conf`	Sequential circuit test generation using dynamic state traversal. ED&TC Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1997	Misc	`conf`	Static logic implication with application to redundancy identification. VTS Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel
1996	J	`jnl`	A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. IEEE Trans. Computers Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi
1996	A	`conf`	A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. ITC Dong Xiang, Janak H. Patel
1996	—	`conf`	Alternating Strategies for Sequential Circuit ATPG. ED&TC Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1996	Misc	`conf`	Automatic test generation using genetically-engineered distinguishing sequences. VTS Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
1996	A	`conf`	Enhancing high-level control-flow for improved testability. ICCAD Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel
1996	Misc	`conf`	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. VTS Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel
1996	J	`jnl`	Hierarchical test generation under architectural level functional constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaushin Lee, Janak H. Patel
1996	Misc	`conf`	Improving accuracy in path delay fault coverage estimation. VLSI Design Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996	—	`conf`	On Double Transition Faults as a Delay Fault Model. Great Lakes Symposium on VLSI Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel
1996	A	`conf`	On Potential Fault Detection in Sequential Circuits. ITC Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz
1996	A*	`conf`	Partial Scan Design Based on Circuit State Information. DAC Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel
1996	A	`conf`	SIGMA: a simulator for segment delay faults. ICCAD Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996	Misc	`conf`	Segment delay faults: a new fault model. VTS Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
1996	A	`conf`	Simulation-based techniques for dynamic test sequence compaction. ICCAD Elizabeth M. Rudnick, Janak H. Patel
1996	—	`conf`	Testability Insertion in Behavioral Descriptions. ISSS Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel
1995	Misc	`conf`	A distance reduction approach to design for testability. VTS Frank F. Hsu, Janak H. Patel
1995	Misc	`conf`	A genetic approach to test application time reduction for full scan and partial scan circuits. VLSI Design Elizabeth M. Rudnick, Janak H. Patel
1995	C	`conf`	A new architectural-level fault simulation using propagation prediction of grouped fault-effects. ICCD Michael S. Hsiao, Janak H. Patel
1995	C	`conf`	A parallel algorithm for fault simulation based on PROOFS . ICCD Steven Parkes, Prithviraj Banerjee, Janak H. Patel
1995	A*	`conf`	Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. DAC Elizabeth M. Rudnick, Janak H. Patel
1995	Misc	`conf`	Cyclic stress tests for full scan circuits. VTS Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel
1995	—	`conf`	Fault Simulation of FTCS Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel
1995	—	`conf`	Overhead reduction techniques for hierarchical fault simulation. Asian Test Symposium Eiji Harada, Janak H. Patel
1995	A*	`conf`	Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. DAC Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel
1995	J	`jnl`	Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. Very Large Scale Integr. Syst. Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel
1994	J	`jnl`	Addressing design for testability at the architectural level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vivek Chickermane, Jaushin Lee, Janak H. Patel
1994	J	`jnl`	An observability enhancement approach for improved testability and at-speed test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
1994	—	`conf`	Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. EDAC-ETC-EUROASIC Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel
1994	J	`jnl`	Architectural level test generation for microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaushin Lee, Janak H. Patel
1994	A	`conf`	Fast timing simulation of transient faults in digital circuits. ICCAD Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel
1994	—	`conf`	Hybrid Resource Management Algorithms for Multicomputer Systems. IPPS Jeff Baxter, John W. C. Fu, Balkrishna Ramkumar, Janak H. Patel
1994	C	`conf`	Latch Design for Transient Pulse Tolerance. ICCD Hungse Cha, Janak H. Patel
1994	A*	`conf`	Microprocessor Testing: Which Technique is Best? (Panel). DAC Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
1994	A*	`conf`	ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation. DAC Steven Parkes, Prithviraj Banerjee, Janak H. Patel
1994	A*	`conf`	Sequential Circuit Test Generation in a Genetic Algorithm Framework. DAC Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
1994	—	`conf`	Trace Driven Simulation using Sampled Traces. HICSS (1) John W. C. Fu, Janak H. Patel
1993	—	`conf`	A Fast and Accurate Gate-Level Transient Fault Simulation Environment. FTCS Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer
1993	C	`conf`	A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. ICCD Hungse Cha, Janak H. Patel
1993	J	`jnl`	An architectural level test generator based on nonlinear equation solving. J. Electron. Test. Jaushin Lee, Janak H. Patel
1993	C	`conf`	Efficient Variable Ordering Heuristics for Shared ROBDD. ISCAS Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel
1993	A	`conf`	Fast and Accurate CMOS Bridging Fault Simulation. ITC Jeff Rearick, Janak H. Patel
1993	Misc	`conf`	Impact of high level functional constraints on testability. VTS Jaushin Lee, Vivek Chickermane, Janak H. Patel
1993	—	`conf`	Memory Reference Behavior of Compiler Optimized Programs on High Speed. ICPP (2) John W. C. Fu, Janak H. Patel
1993	J	`jnl`	NETRA: A Hierarchical and Partitionable Architecture for Computer Vision Systems. IEEE Trans. Parallel Distributed Syst. Alok N. Choudhary, Janak H. Patel, Narendra Ahuja
1993	A*	`conf`	Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel
1993	Misc	`conf`	Testability analysis based on structural and behavioral information. VTS Jaushin Lee, Janak H. Patel
1993	—	`conf`	Theory and Practice of Sequential Machine Testing and Testability. FTCS Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel
1992	A	`conf`	A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD Vivek Chickermane, Jaushin Lee, Janak H. Patel
1992	A*	`conf`	APT: An Area-Performance-Testability Driven Placement Algorithm. DAC Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel
1992	A	`conf`	An Instruction Sequence Assembling Methodology for Testing Microprocessors. ITC Jaushin Lee, Janak H. Patel
1992	J	`jnl`	An efficient design of embedded memories and their testability analysis using Markov chains. J. Electron. Test. Pinaki Mazumder, Janak H. Patel
1992	A	`conf`	Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu
1992	—	`conf`	Compile Time Parallel Resource Allocation for Unbounded Tree Structure Task Graphs. ICPP (1) Jeff Baxter, Balkrishna Ramkumar, Janak H. Patel
1992	A	`conf`	Design for Testability Using Architectural Descriptions. ITC Vivek Chickermane, Jaushin Lee, Janak H. Patel
1992	A	`conf`	Diagnostic Fault Simulation of Sequential Circuits. ITC Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel
1992	A	`conf`	E-PROOFS: a CMOS bridging fault simulator. ICCAD Gary S. Greenstein, Janak H. Patel
1992	A*	`conf`	Hierarchical Test Generation under Intensive Global Functional Constraints. DAC Jaushin Lee, Janak H. Patel
1992	J	`jnl`	PROOFS: a fast, memory-efficient sequential circuit fault simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
1992	Misc	`conf`	Probe point insertion for at-speed test. VTS Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
1992	—	`conf`	Profiling Based Task Migration. IPPS Jeff Baxter, Janak H. Patel
1992	A*	`conf`	Stride directed prefetching in scalar processors. MICRO John W. C. Fu, Janak H. Patel, Bob L. Janssens
1992	J	`jnl`	Test compaction for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham
1991	A	`conf`	A Fault Oriented Partial Scan Design Approach. ICCAD Vivek Chickermane, Janak H. Patel
1991	A	`conf`	A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. ICCAD Jaushin Lee, Janak H. Patel
1991	A	`conf`	ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. ITC Jaushin Lee, Janak H. Patel
1991	—	`conf`	An Architectural Level Test Generator for a Hierarchical Design Environment. FTCS Jaushin Lee, Janak H. Patel
1991	—	`conf`	Data Prefetching Strategies for Vector Cache Memories. IPPS John W. C. Fu, Janak H. Patel
1991	A*	`conf`	Data Prefetching in Multiprocessor Vector Cache Memories. ISCA John W. C. Fu, Janak H. Patel
1991	J	`jnl`	Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors. Digit. Signal Process. Abhijit Chatterjee, Rabindra K. Roy, Jacob A. Abraham, Janak H. Patel
1991	—	`conf`	HITEC: a test generation package for sequential circuits. EURO-DAC Thomas M. Niermann, Janak H. Patel
1991	—	`conf`	How Do We Make Parallel Processing a Reality? Bridging the Gap Between Theory and Practice. IPPS Alfred Brenner, Richard F. Freund, R. Stockton Gaines, Rob Kelly, Louis Lome, Richard McAndrew, Alexandru Nicolau, Janak H. Patel, Thomas Probert, John H. Reif, Jorge L. C. Sanz, Howard Jay Siegel, Jon A. Webb
1991	A	`conf`	Methods for Reducing Events in Sequential Circuit Fault Simulation. ICCAD Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel
1991	A*	`conf`	Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. DAC Srinivas Patil, Prithviraj Banerjee, Janak H. Patel
1990	—	`conf`	A reconfigurable and hierarchical parallel processing architecture: performance results for stereo vision. ICPR (2) Alok N. Choudhary, Subhodev Das, Narendra Ahuja, Janak H. Patel
1990	J	`jnl`	A reconfigurable parallel signature analyzer for concurrent error correction in DRAM. IEEE J. Solid State Circuits Pinaki Mazumder, Janak H. Patel, Jacob A. Abraham
1990	A	`conf`	An optimization based approach to the partial scan design problem. ITC Vivek Chickermane, Janak H. Patel
1990	J	`jnl`	Error Recovery in Shared Memory Multiprocessors Using Private Caches. IEEE Trans. Parallel Distributed Syst. Kun-Lung Wu, W. Kent Fuchs, Janak H. Patel
1990	—	`conf`	PROOFS: a super fast fault simulator for sequential circuits. EURO-DAC Wu-Tung Cheng, Janak H. Patel
1990	—	`conf`	Parallel implementation and evaluation of motion estimation system algorithms on a distributed memory multiprocessor using knowledge based mappings. ICPR (2) Alok N. Choudhary, Mun K. Leung, Thomas S. Huang, Janak H. Patel
1990	—	`conf`	Performance Evaluation of Clusters of NETRA: An Architecture for Computer Vision Systems. ICPP (1) Alok N. Choudhary, Janak H. Patel
1990	A*	`conf`	Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. DAC Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
1989	A*	`conf`	A Functional-Level Test Generation Methodology Using Two-level Representations. DAC Utpal J. Davé, Janak H. Patel
1989	A	`conf`	Accurate logic simulation in the presence of unknowns. ICCAD Susheel J. Chandra, Janak H. Patel
1989	—	`conf`	Cache-Based Error Recovery for Shared Memory Multiprocessor Systems. ICPP (1) Kun-Lung Wu, W. Kent Fuchs, Janak H. Patel
1989	J	`jnl`	Diagnosis and Repair of Memory with Coupling Faults. IEEE Trans. Computers Ming-Feng Chang, W. Kent Fuchs, Janak H. Patel
1989	J	`jnl`	Experimental evaluation of testability measures for test generation (logic circuits). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Susheel J. Chandra, Janak H. Patel
1989	A	`conf`	Load balancing and task decomposition techniques for parallel implementation of integrated vision systems algorithms. SC Alok N. Choudhary, Janak H. Patel
1989	J	`jnl`	Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories. IEEE Trans. Computers Pinaki Mazumder, Janak H. Patel
1989	—	`conf`	The LAST Algorithm: A Heuristic-Based Static Task Allocation Algorithm. ICPP (2) Jeff Baxter, Janak H. Patel
1988	—	`conf`	A Parallel Processing Architecture for an Integrated Vision System. ICPP (1) Alok N. Choudhary, Janak H. Patel
1988	J	`jnl`	Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems. IEEE Trans. Computers Subhasis Laha, Janak H. Patel, Ravishankar K. Iyer
1988	A	`conf`	Compaction of ATPG-generated test sequences for sequential circuits. ICCAD Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh
1988	A	`conf`	Diagnosis and repair of memory with coupling faults. ICCAD Ming-Feng Chang, W. Kent Fuchs, Janak H. Patel
1988	J	`jnl`	Methodologies for testing embedded content addressable memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs
1988	A*	`conf`	Performance Evaluation of On-Chip Register and Cache Organizations. ISCA Richard J. Eickemeyer, Janak H. Patel
1988	C	`conf`	Test generation in a parallel processing environment. ICCD Susheel J. Chandra, Janak H. Patel
1987	A*	`conf`	A Hierarchical Approach Test Vector Generation. DAC Susheel J. Chandra, Janak H. Patel
1987	J	`jnl`	A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. IEEE Trans. Computers Wu-Tung Cheng, Janak H. Patel
1987	A*	`conf`	Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories. DAC Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs
1987	B	`conf`	Parallel Garbage Collection on a Virtual Memory System. ICPP Santosh G. Abraham, Janak H. Patel
1987	A*	`conf`	Performance Evaluation of Multiple Register Sets. ISCA Richard J. Eickemeyer, Janak H. Patel
1986	A*	`conf`	Effectiveness of heuristics measures for automatic test pattern generation. DAC Sanjay J. Patel, Janak H. Patel
1986	A*	`conf`	Performance Measurement of Paging Behavior in Multiprogramming Systems. ISCA Mohammad Malkawi, Janak H. Patel
1985	A*	`conf`	An Efficient LISP-Execution Architecture with a New Representation for List Structures. ISCA Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel
1985	A*	`conf`	Compiler Directed Memory Management Policy For Numerical Programs. SOSP Mohammad Malkawi, Janak H. Patel
1985	A	`conf`	Multiple-Fault Detection in Iterative Logic Arrays. ITC Wu-Tung Cheng, Janak H. Patel
1985	A*	`conf`	Parallel Garbage Collection Without Synchronization Overhead. ISCA Ashwin Ram, Janak H. Patel
1984	A*	`conf`	A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. ISCA Mark S. Papamarcos, Janak H. Patel
1984	A	`conf`	Design of Test Pattern Generators for Built-In Test. ITC Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham
1983	J	`jnl`	Concurrent Error Detection in Multiply and Divide Arrays. IEEE Trans. Computers Janak H. Patel, Leona Y. Fung
1983	A*	`conf`	Performance of Shared Cache for Parallel-Pipelined Computer Systems ISCA Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson
1983	J	`jnl`	Shared Cache for Multiple-Stream Computer Systems. IEEE Trans. Computers Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson
1982	B	`conf`	A performance model for instruction prefetch in pipelined instruction units. ICPP Gregory F. Grohoski, Janak H. Patel
1982	J	`jnl`	Analysis of Multiprocessors with Private Cache Memories. IEEE Trans. Computers Janak H. Patel
1982	J	`jnl`	Concurrent Error Detection in ALU's by Recomputing with Shifted Operands. IEEE Trans. Computers Janak H. Patel, Leona Y. Fung
1982	J	`jnl`	Memory Interference in Synchronous Multiprocessor Systems. IEEE Trans. Computers David W. L. Yen, Janak H. Patel, Edward S. Davidson
1981	J	`jnl`	Performance of Processor-Memory Interconnections for Multiprocessors. IEEE Trans. Computers Janak H. Patel
1980	J	`jnl`	An Alternative to the Distributed Pipeline. IEEE Trans. Computers Janak H. Patel
1979	—	`conf`	PM MARK Faye A. Briggs, King-Sun Fu, Kai Hwang, Janak H. Patel
1979	A*	`conf`	Processor-Memory Interconnections for Multiprocessors. ISCA Janak H. Patel
1978	A*	`conf`	Pipelines wth Internal Buffers. ISCA Janak H. Patel
1976	A*	`conf`	Improving the Throughput of a Pipeline by Insertion of Delays. ISCA Janak H. Patel, Edward S. Davidson