Jan Plíva - RankMe

13 papers C 2Journal 4Unranked 7

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	A Low-Power Fast Settling 5.4 - 8.4 GHz Digitally Controlled Oscillator in 45 nm RFSOI CMOS. MWSCAS Rui Ma, Florian Protze, Jan Plíva, Martin Kreißig, Frank Ellinger
2020	J	`jnl`	Decompressors using nonlinear codes. Microprocess. Microsystems Ondrej Novák, Martin Rozkovec, Jan Plíva
2019	J	`jnl`	A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS. IEEE J. Solid State Circuits László Szilágyi, Jan Plíva, Ronny Henker, David Schoeniger, Jaroslaw P. Turkiewicz, Frank Ellinger
2019	—	`conf`	A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment. SoCC Tobias Schirmer, Mohammad Mahdi Khafaji, Jan Plíva, Frank Ellinger
2019	C	`conf`	A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver Frontends. VLSI-SoC László Szilágyi, Jan Plíva, Ronny Henker, Frank Ellinger
2019	C	`conf`	Combinational Decompressors with Nonlinear Codes. DSD Ondrej Novák, Martin Rozkovec, Jan Plíva
2019	—	`conf`	Offset-Compensation Systems for Multi-Gbit/s Optical Receivers. VLSI-SoC (Selected Papers) László Szilágyi, Jan Plíva, Ronny Henker
2018	—	`conf`	4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS. OFC Alessandro Cevrero, Ilter Özkaya, Thomas Morf, Thomas Toifl, M. Seifried, Frank Ellinger, Mohammad Mahdi Khafaji, Jan Plíva, Ronny Henker, Nikolay N. Ledentsov, J.-R. Kropp, V. A. Shchukin, M. Zoldak, L. Halmo, I. Eddie, Jaroslaw P. Turkiewicz
2018	J	`jnl`	A 4×45 Gb/s Two-Tap FFE VCSEL Driver in 14-nm FinFET CMOS Suitable for Burst Mode Operation. IEEE J. Solid State Circuits Mohammad Mahdi Khafaji, Guido Belfiore, Jan Plíva, Ronny Henker, Frank Ellinger
2017	—	`conf`	Adaptive high-speed and ultra-low power optical interconnect for data center communications. ICTON Ronny Henker, Thomas Toifl, Alessandro Cevrero, Ilter Oezkaya, Michael Georgiades, Mahdi M. Khafaji, Jan Plíva, Frank Ellinger
2017	—	`conf`	Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS. SoCC Jan Plíva, Mahdi M. Khafaji, László Szilágyi, Ronny Henker, Frank Ellinger
2016	J	`jnl`	Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. IEEE J. Solid State Circuits Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2014	—	`conf`	A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm A-SSCC Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici