Jan Moritz Joseph

69 papers A* 1A 4B 2C 4Misc 1Journal 25Unranked 32
YearRankTypeTitle / Venue / Authors
2026 J jnl
Mixed-Precision Training and Compilation for RRAM-based Computing-in-Memory Accelerators.
CoRR
Rebecca Pelke, Joel Klein, José Cubero-Cascante, Nils Bosbach, Jan Moritz Joseph, Rainer Leupers
2025 J jnl
CIMFlow: Modelling Dataflow in Cross-Layer Compute-in-Memory Deep Learning Accelerators.
ACM Trans. Embed. Comput. Syst.
José Cubero-Cascante, Lucas Tonini Rosenberg Schneider, Rebecca Pelke, Arunkumar Vaidyanathan, Rainer Leupers, Jan Moritz Joseph
2025 — conf
EXAMINER: IP Extraction Algorithm from MAGIC Logic-in-Memory.
ISVLSI
Lorenzo Pfeifer, Rainer Leupers, Jan Moritz Joseph
2025 — conf
Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory Accelerators.
ISVLSI
José Cubero-Cascante, Rebecca Pelke, Noah Flohr, Arunkumar Vaidyanathan, Rainer Leupers, Jan Moritz Joseph
2025 J jnl
It's Getting Hot in Here: Hardware Security Implications of Thermal Crosstalk on ReRAMs.
IEEE Trans. Reliab.
Felix Staudigl, Hazem Al Indari, Daniel Schön, Hsin-Yu Chen, Dominik Sisejkovic, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Amelie Hagelauer, Rainer Leupers
2025 J jnl
Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer.
CoRR
Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Niklas Degener, Florian Idrizi, Lennart M. Reimann, Jan Moritz Joseph, Rainer Leupers
2024 — conf
A Calibratable Model for Fast Energy Estimation of MVM Operations on RRAM Crossbars.
AICAS
José Cubero-Cascante, Arunkumar Vaidyanathan, Rebecca Pelke, Lorenzo Pfeifer, Rainer Leupers, Jan Moritz Joseph
2024 — conf
A Fully Automated Platform for Evaluating ReRAM Crossbars.
LATS
Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Letícia Maria Veiras Bolzani, Rainer Leupers, Jan Moritz Joseph
2024 J jnl
A Fully Automated Platform for Evaluating ReRAM Crossbars.
CoRR
Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Leticia Bolzani Poehls, Rainer Leupers, Jan Moritz Joseph
2024 — conf
Analysis of Thermal Side-Channel Attacks on Analog/Digital Computing-in-Memory Accelerators.
LATS
Lorenzo Pfeifer, M. Gross, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2024 A conf
CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures.
DATE
Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2024 J jnl
CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures.
CoRR
Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2024 — conf
NVM-Flip: Non-Volatile-Memory BitFlips on the System Level.
SAT-CPS@CODASPY
Felix Staudigl, Jan Philipp Thoma, Christian Niesler, Karl J. X. Sturm, Rebecca Pelke, Dominik Germek, Jan Moritz Joseph, Tim Güneysu, Lucas Davi, Rainer Leupers
2023 A conf
AIrchitect: Automating Hardware Architecture and Mapping Optimization.
DATE
Ananda Samajdar, Jan Moritz Joseph, Tushar Krishna
2023 — conf
Architecture-Compiler Co-design for ReRAM-Based Multi-core CIM Architectures.
VLSI-SoC (Selected Papers)
Rebecca Pelke, Nils Bosbach, Niklas Degener, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2023 C conf
Efficient RISC-V-on-x64 Floating Point Simulation.
ICCD
Niko Zurstraßen, Nils Bosbach, Jan Moritz Joseph, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers
2023 A* conf
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware.
DAC
Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers
2023 J jnl
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware.
CoRR
Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Leticia Bolzani Poehls, Rainer Leupers
2023 — conf
Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware.
LATS
Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Veiras Bolzani Poehls, Rainer Leupers
2023 C conf
Mapping of CNNs on multi-core RRAM-based CIM architectures.
VLSI-SoC
Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2023 J jnl
Mapping of CNNs on multi-core RRAM-based CIM architectures.
CoRR
Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2023 Misc conf
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories.
CODES+ISSS
Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers
2023 J jnl
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories.
CoRR
Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers
2023 A conf
par-gem5: Parallelizing gem5's Atomic Mode.
DATE
Niko Zurstraßen, José Cubero-Cascante, Jan Moritz Joseph, Li Yichao, Xinghua Xie, Rainer Leupers
2023 — conf
parti-gem5: gem5's Timing Mode Parallelised.
SAMOS
José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller, Rainer Leupers, Jan Moritz Joseph
2023 J jnl
parti-gem5: gem5's Timing Mode Parallelised.
CoRR
José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller, Rainer Leupers, Jan Moritz Joseph
2022 B conf
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs.
FPL
Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph
2022 J jnl
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs.
CoRR
Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph
2022 C conf
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool.
VLSI-SoC
Nils Bosbach, Jan Moritz Joseph, Rainer Leupers, Lukas Jünger
2022 J jnl
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool.
CoRR
Nils Bosbach, Lukas Jünger, Jan Moritz Joseph, Rainer Leupers
2022 A conf
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories.
DATE
Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
2022 J jnl
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs.
ACM Trans. Model. Comput. Simul.
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García-Ortiz, Thilo Pionteck
2022 — conf
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation.
AICAS
Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers
2022 J jnl
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation.
CoRR
Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers
2021 J jnl
AIRCHITECT: Learning Custom Architecture Design and Mapping Space.
CoRR
Ananda Samajdar, Jan Moritz Joseph, Matthew Denton, Tushar Krishna
2021 — conf
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.
ISQED
Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
2021 — conf
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures.
ASP-DAC
Jan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto García-Ortiz, Tushar Krishna, Thilo Pionteck
2021 — conf
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI.
NOCS
Jan Moritz Joseph, Murat Sezgin Baloglu, Yue Pan, Rainer Leupers, Lennart Bamberg
2021 J jnl
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories.
CoRR
Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
2021 — conf
Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies.
NANOCOM
Lennart Bamberg, Tushar Krishna, Jan Moritz Joseph
2020 B conf
A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim.
ISPASS
Ananda Samajdar, Jan Moritz Joseph, Yuhao Zhu, Paul N. Whatmough, Matthew Mattina, Tushar Krishna
2020 J jnl
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.
CoRR
Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
2020 — conf
Optimising Operator Sets for Analytical Database Processing on FPGAs.
ARC
Anna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck
2019 — conf
Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips.
MOCAST
Jan Moritz Joseph, Dominik Ermel, Tobias Drewes, Lennart Bamberg, Alberto García-Ortiz, Thilo Pionteck
2019 J jnl
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment.
Integr.
Lennart Bamberg, Jan Moritz Joseph, Thilo Pionteck, Alberto García Ortiz
2019 J jnl
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures.
IEEE Access
Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García Ortiz, Thilo Pionteck
2019 J jnl
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures.
CoRR
Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García-Ortiz, Thilo Pionteck
2019 J jnl
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs.
CoRR
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García Ortiz, Thilo Pionteck
2019 J jnl
Simulation environment for link energy estimation in networks-on-chip with virtual channels.
Integr.
Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz
2019 — conf
Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models.
FPT
Daniele Passaretti, Jan Moritz Joseph, Thilo Pionteck
2019 C conf
System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips.
ICCD
Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck
2019 J jnl
System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips.
CoRR
Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck
2018 — conf
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels.
PATMOS
Lennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz
2018 — conf
Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs.
FPT
Tobias Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck
2018 — conf
Hardware-Accelerated Index Construction for Semantic Web.
FPT
Christopher Blochwitz, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck
2018 — conf
Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs.
ReCoSoC
Jan Moritz Joseph, Lennart Bamberg, Gerald Krell, Imad Hajjar, Alberto García Ortiz, Thilo Pionteck
2017 — conf
An FPGA-based prototyping framework for Networks-on-Chip.
ReConFig
Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck
2017 J jnl
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs.
Microprocess. Microsystems
Jan Moritz Joseph, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck
2017 — conf
Continuous live-tracing as debugging approach on FPGAs.
ReConFig
Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck
2017 — conf
Design method for asymmetric 3D interconnect architectures with high level models.
ReCoSoC
Jan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto García Ortiz, Thilo Pionteck
2017 — conf
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS.
ReConFig
Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck
2017 — conf
Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications.
ARCS
Christopher Blochwitz, Julian Wolff, Jan Moritz Joseph, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck
2016 — conf
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip.
ReCoSoC
Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck
2016 — conf
Adaptive allocation of default router paths in Network-on-Chips for latency reduction.
HPCS
Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck
2016 — conf
Hardware-accelerated pose estimation for embedded systems using Vivado HLS.
ReConFig
Jan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck
2015 — conf
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases.
ReConFig
Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Thilo Pionteck, Stefan Werner, Dennis Heinrich, Sven Groppe
2015 — conf
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs.
NORCAS
Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck, Alberto García Ortiz
2014 — conf
A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling.
ISSoC
Jan Moritz Joseph, Thilo Pionteck
2014 J jnl
A model for dynamical evolution of science in space.
CoRR
Jan Moritz Joseph, Jens Christian Claussen