Jan Lappas

20 papers A 1B 2C 3Journal 6Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
AnaCraft: Duel-Play Probabilistic-Model-Based Reinforcement Learning for Sample-Efficient PVT-Robust Analog Circuit Sizing Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mohsen Ahmadzadeh, Jan Lappas, Norbert Wehn, Georges G. E. Gielen
2025 — conf
A 15 Gb/s Single-Ended Active-Inductive Equalizer with an Optimized Gain-Enhancing Technique.
NewCAS
Mohammadreza Esmaeilpour, Marco Mestice, Jan Lappas, Christian Weis, Norbert Wehn
2025 — conf
A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology.
SOCC
Marco Mestice, Johannes Feldmann, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn
2025 C conf
Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables.
DDECS
Hussien Abdo, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn
2025 J jnl
Enhanced LPDDR4X PHY in 12 nm FinFET.
CoRR
Johannes Feldmann, Jan Lappas, Mohammadreza Esmaeilpour, Hussien Abdo, Christian Weis, Norbert Wehn
2024 — conf
A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces.
NorCAS
Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn
2024 — conf
A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces.
NewCAS
Mohammadreza Esmaeilpour, Jan Lappas, Hussien Abdo, Christian Weis, Norbert Wehn
2024 C conf
A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology.
VLSI-SoC
Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn
2024 — conf
A Wide-Range Low-Power Phase Interpolation-Based Delay Line with a Linearity Improvement Technique.
VLSI-SoC (Selected Papers)
Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn
2024 B conf
Timing Analysis beyond Complementary CMOS Logic Styles.
ASPDAC
Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif
2024 — conf
Timing Analysis with Analytical Sensitivity.
ISOCC
Jan Lappas, Norbert Wehn, Sani R. Nassif
2022 J jnl
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chirag Sudarshan, Taha Soliman, Jan Lappas, Christian Weis, Mohammad Hassani Sadi, Matthias Jung, Andre Guntoro, Norbert Wehn
2022 — conf
Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology.
ICECS 2022
André Lucas Chinazzo, Jan Lappas, Christian Weis, Qinhui Huang, Zhihang Wu, Leibin Ni, Norbert Wehn
2022 B conf
Machine learning based soft error rate estimation of pass transistor logic in high-speed communication.
ETS
Zhe Zhang, Jan Lappas, André Lucas Chinazzo, Christian Weis, Zhihang Wu, Leibin Ni, Norbert Wehn, Mehdi B. Tahoori
2022 A conf
Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node.
DATE
Jan Lappas, André Lucas Chinazzo, Christian Weis, ChenYang Xia, Zhihang Wu, Leibin Ni, Norbert Wehn
2021 J jnl
A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.
IEEE Trans. Circuits Syst. II Express Briefs
Chirag Sudarshan, Lukas Steiner, Matthias Jung, Jan Lappas, Christian Weis, Norbert Wehn
2021 J jnl
Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks.
J. Signal Process. Syst.
Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn, Li Cheng
2020 J jnl
Efficient Hardware Architectures for 1D- and MD-LSTM Networks.
J. Signal Process. Syst.
Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn, Li Cheng
2019 — conf
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.
SAMOS
Chirag Sudarshan, Jan Lappas, Christian Weis, Deepak M. Mathew, Matthias Jung, Norbert Wehn
2019 C conf
An In-DRAM Neural Network Processing Engine.
ISCAS
Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn