Jan Craninckx - RankMe

184 papers A* 1A 5B 1C 4Journal 78Unranked 93

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	11.5 A Compact 7b 175GS/s Linearized Time-Interleaved Slope ADC with Switched Input Buffers. ISSCC Ewout Martens, Angelo Parisi, Anirudh Kankuppe, Adam Cooman, Hanyue Li, Steven Van Winckel, Pratap Tumkur Renukaswamy, Lucas Moura Santana, Jorge Lagos, Nereo Markulic, Jan Craninckx
2026	J	`jnl`	A 7-bit 150-GSa/s DAC in 5-nm FinFET CMOS. IEEE J. Solid State Circuits Bart Moeneclaey, Joris Lambrecht, Angelo Parisi, Joris Van Kerrebrouck, Gertjan Coudyzer, Anirudh Kankuppe, Xin Yin, Ewout Martens, Jan Craninckx, Peter Ossieur
2025	J	`jnl`	A Scalable mK DC Demultiplexer With Extremely Low OFF-Leakage CMOS Switches for Biasing of Spin Qubits. IEEE Solid State Circuits Lett. Alican Çaglar, Imri Fattal, Clement Godfrin, Roy Li, Steven Van Winckel, Kristiaan De Greve, Piet Wambacq, Jan Craninckx
2025	J	`jnl`	Guest Editorial TCAS-I Special Issue on the ESSERC 2024 Conference. IEEE Trans. Circuits Syst. I Regul. Pap. Georges G. E. Gielen, Jan Craninckx, Hongyang Jia
2025	—	`conf`	Noise Analysis of Constant-Slope Voltage-to-Time Converters. PRIME Mattia Gerardi, Jorge-Luis Lagos, Piet Wambacq, Jan Craninckx
2024	—	`conf`	22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. ISSCC Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, SeHoon Park, Jorge-Luis Lagos, Nereo Markulic, Jan Craninckx
2024	—	`conf`	A 10GS/s Hierarchical Time-Interleaved ADC for RF-Sampling Applications. VLSI Technology and Circuits Nereo Markulic, Johan Nguyen, Jorge Luis Lagos-Benites, Ewout Martens, Jan Craninckx
2024	J	`jnl`	A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL. IEEE J. Solid State Circuits Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Jan Craninckx
2024	—	`conf`	A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS. VLSI Technology and Circuits Jorge Lagos, Pratap Tumkur Renukaswamy, Nereo Markulic, Ewout Martens, Jan Craninckx
2023	J	`jnl`	A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Rui Paulo Martins, Yan Zhu, Jan Craninckx, Chi-Hang Chan
2023	—	`conf`	A 13-16 GHz Low-Noise Oscillator with Enhanced Tank Energy in 22-nm FDSOI. ESSCIRC Sriram Balamurali, Giovanni Mangraviti, Zhiwei Zhong, Piet Wambacq, Jan Craninckx
2023	—	`conf`	A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. ISSCC Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx
2023	—	`conf`	A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET. MWSCAS Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx
2023	—	`conf`	A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. ESSCIRC Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx
2023	—	`conf`	Calibration Techniques for Optimizing Performance of High-Speed ADCs. CICC Ewout Martens, Nereo Markulic, Jorge Luis Lagos-Benites, Jan Craninckx
2023	J	`jnl`	Design and Analysis of a 4.2 mW 4 K 6-8 GHz CMOS LNA for Superconducting Qubit Readout. IEEE J. Solid State Circuits Alican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
2022	—	`conf`	A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout. ESSCIRC Steven Van Winckel, Alican Çaglar, Benjamin Gys, Steven Brebels, Anton Potocnik, Bertrand Parvais, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. IEEE J. Solid State Circuits Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
2022	J	`jnl`	A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS. IEEE J. Solid State Circuits Anirudh Kankuppe, SeHoon Park, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Siddhartha Sinha, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	A Compact, Low-Power Analog Front-End With Event-Driven Input Biasing for High-Density Neural Recording in 22-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs Xiaohua Huang, Marco Ballini, Shiwei Wang, Beatrice Miccoli, Chris Van Hoof, Georges G. E. Gielen, Jan Craninckx, Nick Van Helleputte, Carolina Mora Lopez
2022	J	`jnl`	A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS. IEEE J. Solid State Circuits SeHoon Park, Dae-Woong Park, Kristof Vaesen, Anirudh Kankuppe, Siddhartha Sinha, Barend van Liempd, Piet Wambacq, Jan Craninckx
2022	J	`jnl`	Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS. IEEE J. Solid State Circuits Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx
2022	—	`conf`	Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements. VLSI Technology and Circuits Rohith Acharya, Anton Potocnik, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu
2021	J	`jnl`	A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2021	—	`conf`	A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
2021	J	`jnl`	A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
2021	—	`conf`	A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout. A-SSCC Alican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx
2021	—	`conf`	A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2021	—	`conf`	A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS. ESSCIRC Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx
2021	—	`conf`	A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS. ESSCIRC Anirudh Kankuppe, SeHoon Park, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Piet Wambacq, Jan Craninckx
2021	—	`conf`	A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW. VLSI Circuits Ewout Martens, Davide Dermit, Mithlesh Shrivas, Shun Nagata, Jan Craninckx
2021	J	`jnl`	A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs Keigo Bunsen, Ewout Martens, Davide Dermit, Jan Craninckx
2021	—	`conf`	An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4 VLSI Circuits Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
2021	J	`jnl`	Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2021	C	`conf`	Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. ISCAS Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
2021	—	`conf`	Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing. VLSI Circuits Iuliana P. Radu, Roy Li, Anton Potocnik, Tsvetan Ivanov, Danny Wan, Stefan Kubicek, Nard I. Dumoulin Stuyck, Jeroen Verjauw, Julien Jussot, Yann Canvel, Clement Godfrin, Massimo Mongillo, Rohith Acharya, Asser Elsayed, Mohamed Shehata, Xiaoyu Piao, Antoine Pacco, Laurent Souriau, Sebastien Couet, B. T. Chan, Jan Craninckx, Bertrand Parvais, Alexander Grill, Subramanian Narasimhamoorthy, Steven Van Winckel, Steven Brebels, Fahd A. Mohiyaddin, George Simion, Bogdan Govoreanu
2020	—	`conf`	16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
2020	—	`conf`	17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. ISSCC Pratap Tumkur Renukaswamy, Nereo Markulic, SeHoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx
2020	—	`conf`	A 1 IEEE SENSORS Toshio Yasue, Fortunato Frazzica, Annachiara Spagnolo, David San Segundo Bello, Maarten De Bock, Piet Wambacq, Jan Craninckx
2020	J	`jnl`	A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. IEEE J. Solid State Circuits Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
2020	—	`conf`	A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2020	J	`jnl`	Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. IEEE J. Solid State Circuits Cheng-Hsueh Tsai, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq
2019	J	`jnl`	A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2019	—	`conf`	A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter. ESSCIRC Cheng-Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq
2019	—	`conf`	A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
2019	J	`jnl`	A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
2019	—	`conf`	A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
2019	J	`jnl`	A Compact Quad-Shank CMOS Neural Probe With 5, 120 Addressable Recording Sites and 384 Fully Differential Parallel Channels. IEEE Trans. Biomed. Circuits Syst. Shiwei Wang, Carolina Mora Lopez, Seyed Kasra Garakoui, Ho Sung Chun, Didac Gomez Salinas, Wim Sijbers, Jan Putzeys, Ewout Martens, Jan Craninckx, Nick Van Helleputte
2019	J	`jnl`	A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth. IEEE J. Solid State Circuits Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx
2019	—	`conf`	A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error. ISSCC Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx
2019	J	`jnl`	A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2019	J	`jnl`	Message From the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits Jan Craninckx
2019	—	`conf`	Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper). CICC Aritra Banerjee, Kristof Vaesen, Akshay Visweswaran, Khaled Khalaf, Qixian Shi, Steven Brebels, Davide Guermandi, Cheng-Hsueh Tsai, Johan Nguyen, Alaa Medra, Yao Liu, Giovanni Mangraviti, Orges Furxhi, Bert Gyselinckx, André Bourdoux, Jan Craninckx, Piet Wambacq
2019	J	`jnl`	New Associate Editors. IEEE J. Solid State Circuits Jan Craninckx
2018	—	`conf`	A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
2018	—	`conf`	A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
2018	J	`jnl`	A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. IEEE J. Solid State Circuits Ewout Martens, Benjamin P. Hershberg, Jan Craninckx
2018	J	`jnl`	A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA. IEEE J. Solid State Circuits Gengzhen Qi, Barend van Liempd, Pui-In Mak, Rui Paulo Martins, Jan Craninckx
2018	J	`jnl`	Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification. Sensors Lin-Kun Wu, David San Segundo Bello, Philippe Coppejans, Jan Craninckx, Andreas Süss, Maarten Rosmeulen, Piet Wambacq, Jonathan Borremans
2018	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Jan Craninckx
2018	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Jan Craninckx
2018	J	`jnl`	New Associate Editors. IEEE J. Solid State Circuits Jan Craninckx
2017	—	`conf`	A 2×14bit digital transmitter with memoryless current unit cells and integrated AM/PM calibration. ESSCIRC Mark Ingels, Davide Dermit, Yao Liu, Hans Cappelle, Jan Craninckx
2017	J	`jnl`	A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS. IEEE J. Solid State Circuits Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, Ilja Ocket, André Bourdoux, Piet Wambacq, Jan Craninckx, Wim Van Thillo
2017	—	`conf`	F2: High-performance frequency generation for wireless and wireline systems. ISSCC Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx
2017	J	`jnl`	Introducing Our Sister Publication: IEEE Solid-State Circuits Letters. IEEE J. Solid State Circuits John R. Long, Jan Craninckx, Behzad Razavi
2017	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Jan Craninckx
2017	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Jan Craninckx
2017	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Jan Craninckx
2017	—	`conf`	Session 18 overview: Full duplex wireless front-ends. ISSCC Alyosha C. Molnar, Jan Craninckx, Aarno Pärssinen
2016	—	`conf`	13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise. ISSCC Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
2016	—	`conf`	20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. ISSCC Benjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	50th Anniversary of the Journal. IEEE J. Solid State Circuits Jan Craninckx
2016	—	`conf`	9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
2016	J	`jnl`	A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
2016	—	`conf`	A Fractional-n subsampling PLL based on a digital-to-time converter. MIPRO Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
2016	—	`conf`	EE2: Do we need to downscale our radios below 20nm? ISSCC Harish Krishnaswamy, Jan Craninckx, Tae Wook Kim
2016	—	`conf`	F3: Radio architectures and circuits towards 5G. ISSCC Stefano Pellerano, Ahmad Mirzaei, Chih-Ming Hung, Jan Craninckx, Kenichi Okada, Vojkan Vidojkovic
2016	J	`jnl`	Message From the Incoming Editor-in-Chief. IEEE J. Solid State Circuits Jan Craninckx
2015	—	`conf`	2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS. ISSCC Barend van Liempd, Benjamin P. Hershberg, Kuba Raczkowski, Saneaki Ariumi, Udo Karthaus, Karl-Frederik Bink, Jan Craninckx
2015	—	`conf`	9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise. ISSCC Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
2015	—	`conf`	A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. ESSCIRC Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx
2015	—	`conf`	A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5 ESSCIRC Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
2015	J	`jnl`	A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. IEEE J. Solid State Circuits Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx
2015	J	`jnl`	A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. IEEE J. Solid State Circuits Kuba Raczkowski, Nereo Markulic, Benjamin P. Hershberg, Jan Craninckx
2015	J	`jnl`	An Incremental-Charge-Based Digital Transmitter With Built-in Filtering. IEEE J. Solid State Circuits Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
2015	—	`conf`	An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. ESSCIRC Barend van Liempd, Benjamin P. Hershberg, Björn Debaillie, Piet Wambacq, Jan Craninckx
2015	J	`jnl`	Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". IEEE J. Solid State Circuits Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
2015	—	`conf`	Flicker noise upconversion mechanisms in K-band CMOS VCOs. A-SSCC Qixian Shi, Davide Guermandi, Jan Craninckx, Piet Wambacq
2015	—	`conf`	In-band full-duplex transceiver technology for 5G mobile networks. ESSCIRC Björn Debaillie, Barend van Liempd, Benjamin P. Hershberg, Jan Craninckx, Kari Rikkinen, D. J. van den Broek, Eric A. M. Klumperink, Bram Nauta
2015	J	`jnl`	Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers. J. Signal Process. Syst. Chunshu Li, Min Li, Khaled Khalaf, André Bourdoux, Marian Verhelst, Mark Ingels, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre, Sofie Pollin
2014	—	`conf`	14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS. ISSCC Vito Giannini, Davide Guermandi, Qixian Shi, Kristof Vaesen, Bertrand Parvais, Wim Van Thillo, André Bourdoux, Charlotte Soens, Jan Craninckx, Piet Wambacq
2014	J	`jnl`	A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration. IEEE J. Solid State Circuits Barend van Liempd, Jonathan Borremans, Ewout Martens, Sungwoo Cha, Hans Suys, Bob Verbruggen, Jan Craninckx
2014	—	`conf`	A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. ESSCIRC Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
2014	J	`jnl`	A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. IEEE J. Solid State Circuits Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
2014	—	`conf`	A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS. VLSIC Bob Verbruggen, Kazuaki Deguchi, Badr Malki, Jan Craninckx
2014	—	`conf`	A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction. ESSCIRC Benjamin P. Hershberg, Kuba Raczkowski, Kristof Vaesen, Jan Craninckx
2014	—	`conf`	A Full-Duplex Transceiver Prototype with In-System Automated Tuning of the RF Self-Interference Cancellation. 5GU Mina Mikhael, Barend van Liempd, Jan Craninckx, Rafik Guindi, Björn Debaillie
2014	—	`conf`	A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. ESSCIRC Badr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx
2014	—	`conf`	A dual-notch +27dBm Tx-power electrical-balance duplexer. ESSCIRC Barend van Liempd, Jan Craninckx, R. Singh, Patrick Reynaert, Satoshi Malotaux, John R. Long
2014	—	`conf`	A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3. ESSCIRC Mark Ingels, Xiaoqiang Zhang, Kuba Raczkowski, Sungwoo Cha, Pieter Palmers, Jan Craninckx
2014	J	`jnl`	Analog/RF Solutions Enabling Compact Full-Duplex Radios. IEEE J. Sel. Areas Commun. Björn Debaillie, Dirk-Jan van den Broek, Cristina Lavin, Barend van Liempd, Eric A. M. Klumperink, Carmen Palacios, Jan Craninckx, Bram Nauta, Aarno Pärssinen
2014	—	`conf`	RF self-interference cancellation for full-duplex. CrownCom Barend van Liempd, Björn Debaillie, Jan Craninckx, Cristina Lavin, Carmen Palacios, Satoshi Malotaux, John R. Long, D. J. van den Broek, Eric A. M. Klumperink
2013	J	`jnl`	A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Vincenzo Chironi, Björn Debaillie, Stefano D'Amico, Andrea Baschirotto, Jan Craninckx, Mark Ingels
2013	—	`conf`	A multiband 40nm CMOS LTE SAW-less modulator with -60dBc C-IM3. ISSCC Mark Ingels, Yoshikazu Furuta, Xiaoqiang Zhang, Sungwoo Cha, Jan Craninckx
2013	—	`conf`	IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm. CICC Barend van Liempd, Jonathan Borremans, Sungwoo Cha, Ewout Martens, Hans Suys, Jan Craninckx
2013	—	`conf`	Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited). SiPS Min Li, Khaled Khalaf, Chunshu Li, Vojkan Vidojkovic, Mark Ingels, André Bourdoux, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre
2012	J	`jnl`	A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Masao Iriguchi, Jan Craninckx
2012	—	`conf`	A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. ISSCC Bob Verbruggen, Masao Iriguchi, Jan Craninckx
2012	J	`jnl`	A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli, Jan Craninckx, Geert Van der Plas
2012	—	`conf`	A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. ISSCC Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
2012	—	`conf`	A CMOS IQ Digital Doherty Transmitter using modulated tuning capacitors. ESSCIRC Wagdy M. Gaber, Piet Wambacq, Jan Craninckx, Mark Ingels
2012	J	`jnl`	CMOS software-defined radio transceivers: Analog design in digital technology. IEEE Commun. Mag. Jan Craninckx
2012	A	`conf`	Design of an intrinsically-linear double-VCO-based ADC with 2 DATE Peng Gao, Xinpeng Xing, Jan Craninckx, Georges G. E. Gielen
2012	J	`jnl`	RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert
2011	J	`jnl`	A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers. IEEE J. Solid State Circuits Jonathan Borremans, Gunjan Mandal, Vito Giannini, Björn Debaillie, Mark Ingels, Tomohiro Sano, Bob Verbruggen, Jan Craninckx
2011	—	`conf`	A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers. ISSCC Jonathan Borremans, Gunjan Mandal, Vito Giannini, Tomohiro Sano, Mark Ingels, Bob Verbruggen, Jan Craninckx
2011	—	`conf`	A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter. ESSCIRC Wagdy M. Gaber, Piet Wambacq, Jan Craninckx, Mark Ingels
2011	—	`conf`	A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS. ISSCC Vito Giannini, Mark Ingels, Tomohiro Sano, Björn Debaillie, Jonathan Borremans, Jan Craninckx
2011	—	`conf`	A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration. ESSCIRC Kameswaran Vengattaramane, Jonathan Borremans, Michiel Steyaert, Jan Craninckx
2011	—	`conf`	An impedance modulated class-E polar amplifier in 90 nm CMOS. A-SSCC Mark Ingels, Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx
2011	—	`ch.`	Low-Power ADCs for Bio-Medical Applications. Bio-Medical CMOS ICs Jan Craninckx, Geert Van der Plas
2011	—	`conf`	SAW-less software-defined radio transceivers in 40nm CMOS. CICC Jan Craninckx, Jonathan Borremans, Mark Ingels
2010	J	`jnl`	A 0.5 mm IEEE J. Solid State Circuits Arnd Geis, Julien Ryckaert, Lynn Bos, Gerd Vandersteen, Yves Rolain, Jan Craninckx
2010	J	`jnl`	A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2010	—	`conf`	A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. ISSCC Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2010	J	`jnl`	A 5 mm IEEE J. Solid State Circuits Mark Ingels, Vito Giannini, Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx
2010	—	`conf`	A 5mm ISSCC Mark Ingels, Vito Giannini, Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx
2010	J	`jnl`	A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS. IEEE J. Solid State Circuits Jonathan Borremans, Kameswaran Vengattaramane, Vito Giannini, Björn Debaillie, Wim Van Thillo, Jan Craninckx
2010	—	`conf`	A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS. ISSCC Jonathan Borremans, Kameswaran Vengattaramane, Kameswaran Giannini, Jan Craninckx
2010	J	`jnl`	A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS. IEEE J. Solid State Circuits Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx
2010	A	`conf`	A compact digital amplitude modulator in 90nm CMOS. DATE Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx, Mark Ingels
2010	—	`conf`	A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point. ESSCIRC Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Vito Giannini, Jan Craninckx
2010	A	`conf`	An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation. DATE Arnd Geis, Pierluigi Nuzzo, Julien Ryckaert, Yves Rolain, Gerd Vandersteen, Jan Craninckx
2010	C	`conf`	An area efficient digital amplitude modulator in 90nm CMOS. ISCAS Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx, Mark Ingels
2010	—	`conf`	Reconfigurable RF and data converters. ISSCC Stefan Heinen, Domine Leenaerts, Trudy Stetzler, Yiannos Manoli, Jan Craninckx, Ali Niknejad, Didier Belot, Raf Roovers, K. P. Pun, Jed Hurwitz
2009	J	`jnl`	A 2-mm IEEE J. Solid State Circuits Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Jonathan Borremans, Joris Van Driessche, Jan Craninckx, Mark Ingels
2009	J	`jnl`	A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2009	J	`jnl`	A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. IEEE J. Solid State Circuits Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx, Geert Van der Plas
2009	—	`conf`	A 2mm ISSCC Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Michiel Steyaert, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Joris Van Driessche, Jan Craninckx, Mark Ingels
2009	J	`jnl`	A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. IEEE J. Solid State Circuits Jonathan Borremans, Julien Ryckaert, Claude Desset, Maarten Kuijk, Piet Wambacq, Jan Craninckx
2009	A	`conf`	A design methodology for fully reconfigurable Delta-Sigma data converters. DATE Yi Ke, Jan Craninckx, Georges G. E. Gielen
2009	—	`conf`	A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS. ESSCIRC Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx
2009	C	`conf`	Analysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL. ISCAS Kameswaran Vengattaramane, Jan Craninckx, Michiel Steyaert
2009	J	`jnl`	Calibration of Direct-Conversion Transceivers. IEEE J. Sel. Top. Signal Process. Björn Debaillie, Peter Van Wesemael, Gerd Vandersteen, Jan Craninckx
2009	—	`conf`	Clock synthesis design. ISSCC Jan Craninckx
2009	—	`book`	Green Software Defined Radios - Enabling seamless connectivity while saving on hardware and energy Liesbet Van der Perre, Jan Craninckx, Antoine Dejonghe
2008	J	`jnl`	A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized G IEEE Trans. Circuits Syst. II Express Briefs Pieter Crombez, Jan Craninckx, Piet Wambacq, Michiel Steyaert
2008	—	`conf`	A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS. ISSCC Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
2008	J	`jnl`	A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. IEEE J. Solid State Circuits Jonathan Borremans, Andrea Bevilacqua, Stephane Bronckers, Morin Dehan, Maarten Kuijk, Piet Wambacq, Jan Craninckx
2008	J	`jnl`	A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios. IEEE Trans. Circuits Syst. II Express Briefs Yi Ke, Jan Craninckx, Georges G. E. Gielen
2008	J	`jnl`	A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer. IEEE J. Solid State Circuits Willem Laflere, Michiel S. J. Steyaert, Jan Craninckx
2008	—	`conf`	A Single-Inductor Dual-Band VCO in a 0.06mm ISSCC Jonathan Borremans, Stephane Bronckers, Piet Wambacq, Maarten Kuijk, Jan Craninckx
2008	—	`conf`	A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS. ESSCIRC Jonathan Borremans, Julien Ryckaert, Piet Wambacq, Maarten Kuijk, Jan Craninckx
2008	—	`conf`	An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. ISSCC Vito Giannini, Pierluigi Nuzzo, Vincenzo Chironi, Andrea Baschirotto, Geert Van der Plas, Jan Craninckx
2008	—	`conf`	Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum). ISSCC Stefan Heinen, Francesco Svelto, Jan Craninckx, Mototsugu Hamada, Domine Leenaerts, Chris Rudell
2008	—	`conf`	Calibration Method Enabling Low-Cost SDR. ICC Björn Debaillie, Peter Van Wesemael, Jan Craninckx
2008	B	`conf`	Calibration of SDR Circuit Imperfections. GLOBECOM Björn Debaillie, Peter Van Wesemael, Jan Craninckx
2007	J	`jnl`	A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a. IEEE J. Solid State Circuits Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Bart van Poucke, Jan Craninckx
2007	—	`conf`	A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. ISSCC Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx
2007	—	`conf`	A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. ISSCC Jan Craninckx, Geert Van der Plas
2007	—	`conf`	A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier. ESSCIRC Mark Ingels, Charlotte Soens, Jan Craninckx, Vito Giannini, T. Kim, Björn Debaillie, Michael Libois, Michaël Goffioul, Joris Van Driessche
2007	—	`conf`	A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS. ISSCC Jan Craninckx, M. Liu, Dries Hauspie, Vito Giannini, T. Kim, Jaehoon Lee, Mike Libois, Björn Debaillie, Charlotte Soens, Andrea Baschirotto, Joris Van Driessche, Liesbet Van der Perre, Peter Vanbekbergen
2007	—	`conf`	A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS. ESSCIRC Vincent De Heyn, Geert Van der Plas, Julien Ryckaert, Jan Craninckx
2007	—	`conf`	A power amplifier driver using self-oscillating pulse-width modulators. ESSCIRC Willem Laflere, Michiel Steyaert, Jan Craninckx
2007	—	`conf`	Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy. ISSCC Liesbet Van der Perre, Bruno Bougard, Jan Craninckx, Wim Dehaene, Lieven Hollevoet, Murali Jayapala, Pol Marchal, Miguel Miranda, Praveen Raghavan, Thomas Schuster, Piet Wambacq, Francky Catthoor, Peter Vanbekbergen
2007	J	`jnl`	Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends. IEEE J. Solid State Circuits Vito Giannini, Jan Craninckx, Stefano D'Amico, Andrea Baschirotto
2007	J	`jnl`	Green Reconfigurable Radio Systems. IEEE Signal Process. Mag. Antoine Dejonghe, Bruno Bougard, Sofie Pollin, Jan Craninckx, André Bourdoux, Liesbet Van der Perre, Francky Catthoor
2007	—	`conf`	Linearity guidelines for gm-C biquad filter design using architecture optimization with Volterra analysis. ECCTD Pieter Crombez, Jan Craninckx, Piet Wambacq, Michiel Steyaert
2007	—	`conf`	Optimal Design Methodology for High-Order Continuous-Time Wideband Delta-Sigma Converters. ICECS Yi Ke, Soheil Radiom, Hamidreza Rezaee, Guy A. E. Vandenbosch, Jan Craninckx, Georges G. E. Gielen
2007	J	`jnl`	Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size. IEEE J. Solid State Circuits Dries Hauspie, Eun-Chul Park, Jan Craninckx
2006	A	`conf`	A synthesis tool for power-efficient base-band filter design. DATE Vito Giannini, Pierluigi Nuzzo, Fernando De Bernardinis, Jan Craninckx, Boris Come, Stefano D'Amico, Andrea Baschirotto
2006	C	`conf`	Fully reconfigurable active-Gm-RC biquadratic cells for software defined radio applications. ISCAS Vito Giannini, Jan Craninckx, J. Compiet, Boris Come, Stefano D'Amico, Andrea Baschirotto
2005	—	`conf`	A 5-GHz BiCMOS variable-gain low noise amplifier with inductorless low-gain branch. ESSCIRC Mingxu Liu, Jan Craninckx
2004	—	`conf`	A harmonic quadrature LO generator using a 90° delay-locked loop [zero-IF transceiver applications]. ESSCIRC Jan Craninckx, Vincent Gravot, Stéphane Donnay
2003	A*	`conf`	4G terminals: how are we going to design them? DAC Jan Craninckx, Stéphane Donnay
1998	J	`jnl`	A fully integrated CMOS DCS-1800 frequency synthesizer. IEEE J. Solid State Circuits Jan Craninckx, Michel S. J. Steyaert
1997	J	`jnl`	A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors. IEEE J. Solid State Circuits Jan Craninckx, Michiel S. J. Steyaert
1996	J	`jnl`	A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS. IEEE J. Solid State Circuits Jan Craninckx, Michiel S. J. Steyaert
1995	J	`jnl`	A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler. IEEE J. Solid State Circuits Jan Craninckx, Michel S. J. Steyaert
1995	J	`jnl`	A CMOS rectifier-integrator for amplitude detection in hard disk servo loops. IEEE J. Solid State Circuits Michel S. J. Steyaert, Wim Dehaene, Jan Craninckx, Mairtin Walsh, Peter Real