James Patrick Parkerson

17 papers A 1B 2Journal 6Unranked 8
YearRankTypeTitle / Venue / Authors
2019 — conf
Gesture Classification with Low-Cost Capacitive Sensor Array for Upper Extremity Rehabilitation.
IEEE SENSORS
Haoyan Liu, Enrique Sanchez, James Patrick Parkerson, Alexander Nelson
2019 B conf
Poster Abstract: Unobtrusive Sleep Monitoring with Low-Cost Pressure Sensor Array.
CHASE
Haoyan Liu, Enrique Sanchez, James Patrick Parkerson, Alexander Nelson
2018 B conf
Connected Capacitive Sensor Array for Upper-Extremity Motor Rehabilitation.
CHASE
Haoyan Liu, James Patrick Parkerson, Alexander Nelson
2015 J jnl
Perpetuu: A Tiered Solar-powered GIS Microserver.
ACM Trans. Embed. Comput. Syst.
Adam Matthews, Stanislav Bobovych, Nilanjan Banerjee, James Patrick Parkerson, Ryan W. Robucci, Chintan Patel
2015 — conf
SunaPlayer: high-accuracy emulation of solar cells.
IPSN
Stanislav Bobovych, Nilanjan Banerjee, Ryan W. Robucci, James Patrick Parkerson, Jackson Schmandt, Chintan Patel
2014 J jnl
Information Rich GIS Dissemination in Disconnected Environments.
Trans. GIS
William Johnston, Nilanjan Banerjee, Jackson David Cothren, James Patrick Parkerson
2013 A conf
System Support for Micro-Harvester Powered Mobile Sensing.
RTSS
Alexander Nelson, Jackson Schmandt, William Wilkins, James Patrick Parkerson, Nilanjan Banerjee
2012 — conf
Evaluating solar panel-driven systems in the laboratory.
WiNTECH
Stanislav Bobovych, James Patrick Parkerson, Nilanjan Banerjee
2010 J jnl
An Approach for Implementing State Machines with Online Testability.
VLSI Design
Parag K. Lala, Adam Mathews, James Patrick Parkerson
2007 J jnl
Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2006 J jnl
On self-healing digital system design.
Microelectron. J.
Parag K. Lala, B. Kiran Kumar, James Patrick Parkerson
2006 J jnl
Reversible-logic design with online testability.
IEEE Trans. Instrum. Meas.
Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson
2005 — conf
A Technique for Designing Totally Self-Checking Domino Logic Circuits.
ISQED
C. K. Tang, Parag K. Lala, James Patrick Parkerson
2005 — conf
CMOS Realization of Online Testable Reversible Logic Gates.
ISVLSI
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2004 — conf
A Novel Approach for On-line Testable Reversible Logic Circuit Desig.
Asian Test Symposium
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2004 — conf
Logic implementation using a reversible gate.
Circuits, Signals, and Systems
Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala
2004 — conf
Online Testable Reversible Logic Circuit Design using NAND Blocks.
DFT
Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson