James J. Davis

34 papers A 2B 3C 1Misc 4Journal 16Unranked 8

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Enabling Binary Neural Network Training on the Edge. ACM Trans. Embed. Comput. Syst. Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
2023	J	`jnl`	Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Erwei Wang, Marie Auffret, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah, James J. Davis
2022	B	`conf`	FPL Demo: Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation. FPL Marie Auffret, Erwei Wang, James J. Davis
2022	A	`conf`	Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah
2021	J	`jnl`	Digit Stability Inference for Iterative Methods Using Redundant Number Representation. IEEE Trans. Computers He Li, Ian McInerney, James J. Davis, George A. Constantinides
2021	—	`conf`	Enabling Binary Neural Network Training on the Edge. EMDL@MobiSys Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
2021	J	`jnl`	Enabling Binary Neural Network Training on the Edge. CoRR Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides
2021	J	`jnl`	Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah
2020	J	`jnl`	Digit Stability Inference for Iterative Methods Using Redundant Number Representation. CoRR He Li, Ian McInerney, James J. Davis, George A. Constantinides
2020	J	`jnl`	LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. IEEE Trans. Computers Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2020	J	`jnl`	architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute. IEEE Trans. Very Large Scale Integr. Syst. He Li, James J. Davis, John Wickerson, George A. Constantinides
2019	J	`jnl`	ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute. CoRR He Li, James J. Davis, John Wickerson, George A. Constantinides
2019	J	`jnl`	Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
2019	J	`jnl`	Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
2019	J	`jnl`	LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2019	Misc	`conf`	LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2019	J	`jnl`	LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides
2018	Misc	`conf`	A PYNQ-Based Framework for Rapid CNN Prototyping. FCCM Erwei Wang, James J. Davis, Peter Y. K. Cheung
2018	—	`conf`	An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems. PECCS Graeme M. Bragg, Charles Leech, Domenico Balsamo, James J. Davis, Eduardo Wächter, Geoff V. Merrett, George A. Constantinides, Bashir M. Al-Hashimi
2018	C	`conf`	Digit Elision for Arbitrary-accuracy Iterative Computation. ARITH He Li, James J. Davis, John Wickerson, George A. Constantinides
2018	—	`conf`	Hardware Compilation of Deep Neural Networks: An Overview. ASAP Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2018	J	`jnl`	KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2018	—	`conf`	KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017	J	`jnl`	KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017	B	`conf`	STRIPE: Signal selection for runtime power estimation. FPL James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017	J	`jnl`	Voltage, Throughput, Power, Reliability, and Multicore Scaling. Computer Fei Xia, Ashur Rafiev, Ali Aalsaud, Mohammed A. Noaman Al-Hayanni, James J. Davis, Joshua M. Levine, Andrey Mokhov, Alexander B. Romanovsky, Rishad A. Shafik, Alex Yakovlev, Sheng Yang
2017	—	`conf`	architect: Arbitrary-precision constant-hardware iterative compute. FPT He Li, James J. Davis, John Wickerson, George A. Constantinides
2016	Misc	`conf`	KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2016	A	`conf`	Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2016	—	`conf`	Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators. ARC James J. Davis, Peter Y. K. Cheung
2015	—	`conf`	Adaptive energy minimization of embedded heterogeneous systems using regression-based learning. PATMOS Sheng Yang, Rishad A. Shafik, Geoff V. Merrett, Edward A. Stott, Joshua M. Levine, James J. Davis, Bashir M. Al-Hashimi
2014	B	`conf`	Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. FPL James J. Davis, Peter Y. K. Cheung
2014	Misc	`conf`	Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration. FCCM James J. Davis, Peter Y. K. Cheung
2013	—	`conf`	Datapath fault tolerance for parallel accelerators. FPT James J. Davis, Peter Y. K. Cheung