James E. Stine

80 papers A 1C 15Misc 7Journal 8Unranked 49

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Alchemy : A Methodology for Scalable RTL Design Space Exploration. ACM Great Lakes Symposium on VLSI Ryan Swann, James E. Stine
2025	—	`conf`	Design of a Robust IEEE Compliant Floating - Point Divide and Square Root Using Iterative Approximation. LASCAS Carson Sager, James E. Stine
2025	J	`jnl`	Shared Recurrence Floating-Point Divide/Sqrt and Integer Divide/Remainder With Early Termination. IEEE Trans. Computers Kevin Kim, Katherine Parry, David M. Harris, Cedar Turek, Alessandro Maiuolo, Rose Thompson, James E. Stine
2024	—	`conf`	CharLib: An Open Source Standard Cell Library Characterizer. MWSCAS Marcus Mellor, James E. Stine
2024	—	`conf`	Methodologies for Implementation of Standard-Cell Libraries for Radiation Hardened Environments. LASCAS Ryan Ridley, James E. Stine, George Suárez
2024	—	`conf`	Power Reduction of Montgomery Multiplication Architectures Using Clock Gating. MWSCAS Rachana Erra, James E. Stine
2024	J	`jnl`	Unified Digit Selection for Radix-4 Recurrence Division and Square Root. IEEE Trans. Computers David M. Harris, James E. Stine, Milos D. Ercegovac, Alberto Nannarelli, Katherine Parry, Cedar Turek
2023	Misc	`conf`	Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures. ACSSC Alexander Underwood, James E. Stine
2023	J	`jnl`	Evaluation of a Modular Approach to AES Hardware Architecture and Optimization. J. Signal Process. Syst. Ryan Swann, James E. Stine
2023	J	`jnl`	NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine
2023	Misc	`conf`	Parallelization of the Shift and Add Reducer. ACSSC Ryan Swann, James E. Stine
2022	C	`conf`	Implementation of High Performance IEEE 754-Posit Conversion Hardware. ISCAS Brett Mathis, James E. Stine
2022	C	`conf`	Point-Targeted Sparseness and Ling Transforms on Parallel Prefix Adder Trees. ARITH Teodor-Dumitru Ene, James E. Stine
2021	C	`conf`	A Comprehensive Exploration of the Parallel Prefix Adder Tree Space. ICCD Teodor-Dumitru Ene, James E. Stine
2021	—	`conf`	A Reconfigurable Architecture for Improvement and Optimization of Advanced Encryption Standard Hardware. ACSCC Ryan Swann, James E. Stine
2020	—	`conf`	A Ling-Enhanced Adder for IEEE-compliant Floating-Point Multiplication. MWSCAS S. Ross Thompson, James E. Stine
2020	C	`conf`	A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point Multiplier. ICCD S. Ross Thompson, James E. Stine
2020	Misc	`conf`	An Architecture for Improving Variable Radix Real and Complex Division Using Recurrence Division. ACSSC James E. Stine, Milos D. Ercegovac, Jean-Michel Muller
2020	—	`conf`	An Efficient Implementation of Radix-4 Integer Division Using Scaling. MWSCAS James E. Stine, Kevin Hill
2020	—	`conf`	An Improved Hardware Architecture for modulo without Multiplication. MWSCAS Ryan Swann, James E. Stine
2019	—	`conf`	A Low-Power Recurrence-Based Radix 4 Divider Using Signed-Digit Addition. ISVLSI Matthew Gaalswyk, James E. Stine
2019	—	`conf`	A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter. ISVLSI Brett Mathis, James E. Stine
2019	—	`conf`	A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter. ASAP Brett Mathis, James E. Stine
2019	—	`conf`	An Emphasis on Memory and Processor Interactions in Undergraduate Computer Architecture Education. WCAE@ISCA Alexander Underwood, James E. Stine
2019	Misc	`conf`	Conditional Estimation of Residuals with Prescaling for Use in Low-Energy Division Units. ACSSC Milos D. Ercegovac, James E. Stine
2019	C	`conf`	Fast and Area-Efficient SRAM Word-Line Optimization. ISCAS Bin Wu, James E. Stine, Matthew R. Guthaus
2019	—	`conf`	Using Carry Increment Adders to Enhance Energy Savings with Spanning-Tree Adder Structures. MWSCAS Kyle Price, James E. Stine
2018	J	`jnl`	A 64 kB Approximate SRAM Architecture for Low-Power Video Applications. IEEE Embed. Syst. Lett. Samira Ataei, James E. Stine
2018	—	`conf`	A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications. SoCC Samira Ataei, James E. Stine
2018	—	`conf`	Clarifications and Optimizations on Rounding for IEEE-compliant Floating-Point Multiplication. ASAP Tuan D. Nguyen, Son Bui, James E. Stine
2018	Misc	`conf`	Low-Area Memoryless optimized Soft-Decision Viterbi Decoder with Dedicated Paralell Squaring Architecture. ACSSC John D. Tobola, James E. Stine
2017	—	`conf`	A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time. ACM Great Lakes Symposium on VLSI Samira Ataei, James E. Stine
2017	Misc	`conf`	A combined IEEE half and single precision floating point multipliers for deep learning. ACSSC Tuan D. Nguyen, James E. Stine
2017	—	`conf`	A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS. MWSCAS Samira Ataei, Matthew Gaalswyk, James E. Stine
2017	—	`conf`	Constant-based truncated cubing architectures. MWSCAS Son Bui, James E. Stine
2017	—	`conf`	Sustainable IC design and fabrication. IGSC Donald Kline Jr., Nikolas Parshook, Alex Johnson, James E. Stine, William E. Stanchina, Erik Brunvand, Alex K. Jones
2017	—	`conf`	WIP. Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm. MSE Rabin Thapa, Samira Ataei, James E. Stine
2016	C	`conf`	A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. ICCD Samira Ataei, James E. Stine, Matthew R. Guthaus
2016	A	`conf`	OpenRAM: an open-source memory compiler. ICCAD Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar
2016	Misc	`conf`	Optimized multipartite table methods for elementary function computation. ACSSC James E. Stine, Masoud Sadeghian
2015	—	`conf`	A differential single-port 8T SRAM bitcell for variability tolerance and low voltage operation. IGSC Samira Ataei, James E. Stine
2015	—	`conf`	An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbers. ASAP S. Ross Thompson, James E. Stine
2015	—	`conf`	Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers. ACM Great Lakes Symposium on VLSI Samira Ataei, James E. Stine
2015	—	`conf`	Revisiting redundant Booth with bias multipliers. MWSCAS Sampoorna Mallipeddi, James E. Stine
2014	C	`conf`	Additional optimizations for parallel squarer units. ISCAS Son Bui, James E. Stine
2014	C	`conf`	Enhancing the Unified Logical Effort algorithm for branching and load distribution. ISCAS Mehedi Sarwar, James E. Stine
2014	—	`conf`	Experiments with High Speed Parallel Cubing Units. ISVLSI Son Bui, James E. Stine, Masoud Sadeghian
2014	C	`conf`	Optimized cubic chebyshev interpolator for elementary function hardware implementations. ISCAS Masoud Sadeghian, James E. Stine, E. George Walters III
2012	—	`conf`	Elementary function approximation using optimized most significant bits of Chebyshev coefficients and truncated multipliers. MWSCAS Masoud Sadeghian, James E. Stine
2012	—	`conf`	Optimized low-power elementary function approximation for Chebyshev series approximations. ACSCC Masoud Sadeghian, James E. Stine
2012	—	`conf`	Session TA6b: Low power II (invited). ACSCC James E. Stine
2011	C	`conf`	A recursive-divide architecture for multiplication and division. ISCAS James E. Stine, Amey Phadke, Surpriya Tike
2009	—	`conf`	FreePDK v2.0: Transitioning VLSI education towards nanometer variation-aware designs. MSE James E. Stine, Jun Chen, Ivan D. Castellanos, Gopal Sundararajan, Mohammad A. Qayum, Praveen Kumar, Justin Remington, Sohum Sohoni
2009	—	`conf`	Parallel Prefix Ling Structures for Modulo 2^n-1 Addition. ASAP Jun Chen, James E. Stine
2008	—	`conf`	Compressor trees for decimal partial product reduction. ACM Great Lakes Symposium on VLSI Ivan D. Castellanos, James E. Stine
2008	—	`conf`	Session WA5b: Low power methods. ACSCC James E. Stine
2008	—	`conf`	Single-ended half-swing low-power SRAM design. ACSCC Harsha Choday, James E. Stine
2007	—	`conf`	FreePDK: An Open-Source Variation-Aware Design Kit. MSE James E. Stine, Ivan D. Castellanos, Michael H. Wood, Jeff Henson, Fred Love, W. Rhett Davis, Paul D. Franzon, Michael Bucher, Sunil Basavarajaiah, Julie Oh, Ravi Jenkal
2007	—	`conf`	Partial Product Reduction for Parallel Cubing. ISVLSI James E. Stine, Jeff M. Blank
2006	—	`conf`	A 64-bit Decimal Floating-Point Comparator. ASAP Ivan D. Castellanos, James E. Stine
2006	C	`conf`	Compressed symmetric tables for accurate function approximation of reciprocals. ISCAS James E. Stine, Nitin Naresh
2006	—	`conf`	Dual-Mode High-Speed Low-Energy Binary Addition. ISVLSI Johannes Grad, James E. Stine
2006	C	`conf`	Low power binary addition using carry increment adders. ISCAS Johannes Grad, James E. Stine
2005	—	`conf`	A Framework for High-Level Synthesis of System-on-Chip Designs. MSE James E. Stine, Johannes Grad, Ivan D. Castellanos, Jeff M. Blank, Vibhuti B. Dave, Mallika Prakash, Nick Iliev, Nathan Jachimiec
2005	—	`conf`	A combined two's complement and floating-point comparator. ISCAS (1) James E. Stine, Michael J. Schulte
2005	—	`conf`	Constant addition utilizing flagged prefix structures. ISCAS (1) James E. Stine, Christopher R. Babb, Vibhuti B. Dave
2005	—	`conf`	New algorithms for carry propagation. ACM Great Lakes Symposium on VLSI Johannes Grad, James E. Stine
2005	—	`conf`	Real World SOC Experience for the Classroom. MSE Johannes Grad, James E. Stine, David D. Neiman
2004	J	`jnl`	Intrinsic Compiler Support for Interval Arithmetic. Numer. Algorithms Ahmet Akkas, Michael J. Schulte, James E. Stine
2004	—	`conf`	Modified booth truncated multipliers. ACM Great Lakes Symposium on VLSI Alok A. Katkar, James E. Stine
2004	—	`conf`	Parallel Programmable Finite Field GF(2m) Multipliers. ISVLSI Nick Iliev, James E. Stine, Nathan Jachimiec
2003	—	`conf`	A Standard Cell Library for Student Projects. MSE Johannes Grad, James E. Stine
2003	—	`conf`	A pipelined clock-delayed domino carry-lookahead adder. ACM Great Lakes Symposium on VLSI Bhushan A. Shinkre, James E. Stine
2003	C	`conf`	Variations on Truncated Multiplication. DSD James E. Stine, Oliver M. Duverne
2001	C	`conf`	Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. ICCD Kent E. Wires, Michael J. Schulte, James E. Stine
1999	J	`jnl`	Approximating Elementary Functions with Symmetric Bipartite Tables. IEEE Trans. Computers Michael J. Schulte, James E. Stine
1999	J	`jnl`	The Symmetric Table Addition Method for Accurate Function Approximation. J. VLSI Signal Process. James E. Stine, Michael J. Schulte
1998	—	`conf`	A Combined Interval and Floating Point Multiplier. Great Lakes Symposium on VLSI James E. Stine, Michael J. Schulte
1997	—	`conf`	Accurate Function Approximations by Symmetric Table Lookup and Addition. ASAP Michael J. Schulte, James E. Stine
1997	C	`conf`	Symmetric Bipartite Tables for Accurate Function Approximation. IEEE Symposium on Computer Arithmetic Michael J. Schulte, James E. Stine