James D. Warnock

36 papers A* 2A 2C 1Misc 1Journal 21Unranked 9

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	IBM z14 design methodology enhancements in the 14-nm technology node. IBM J. Res. Dev. Christopher J. Berry, James D. Warnock, John Badar, Dean G. Bair, Erwin Behnen, Brian Bell, Alper Buyuktosunoglu, Chris Cavitt, Pierce Chuang, Ofer Geva, Dina Hamid, John Isakson, Preetham Lobo, Frank Malgioglio, Guenter Mayer, José Luis Neves, Thomas Strach, Jesse Surprise, Christos Vezyrtzis, Tobias Webel, David Wolpert
2018	J	`jnl`	IBM z14: Enabling physical design in 14-nm technology for high-performance, high-reliability microprocessors. IBM J. Res. Dev. David Wolpert, Erwin Behnen, Leon J. Sigal, Yuen H. Chan, Gustavo Enrique Téllez, Douglas Bradley, Richard E. Serton, Rajesh Veerabhadraiah, William Ansley, Andrew Bianchi, Nagu Dhanwada, Sungjae Lee, Michael Scheuermann, Glen A. Wiedemeier, John Davis, Tobias Werner, Laura Darden, Keith G. Barkley, Michael Gray, Matthew Guzowski, Mitch DeHond, Timothy Schell, Stelios Tsapepas, Di Phan, Kriti Acharya, Jeffrey A. Zitz, Hunter F. Shi, Christopher J. Berry, James D. Warnock, Michael H. Wood, Robert M. Averill III
2018	—	`conf`	IBM z14™: 14nm microprocessor for the next-generation mainframe. ISSCC Christopher J. Berry, James D. Warnock, John Isakson, John Badar, Brian Bell, Frank Malgioglio, Guenter Mayer, Dina Hamid, Jesse Surprise, David Wolpert, Ofer Geva, Bill Huott, Leon J. Sigal, Sean M. Carey, Richard F. Rizzolo, Ricardo Nigaglioni, Mark Cichanowski, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito, Arthur O'neill, Robert J. Sonnelitter, Christian G. Zoellin, Michael H. Wood, José Neves
2018	Misc	`conf`	Impact of Device Aging on Early Mode Failures in Pulsed Latches. VLSID Ankur Shukla, Rahul M. Rao, James D. Warnock
2016	A	`conf`	Design-synthesis co-optimisation using skewed and tapered gates. DATE Ayan Datta, James D. Warnock, Ankur Shukla, Saurabh Gupta, Yiu H. Chan, Karthik Mohan, Charudhattan Nagarajan
2015	—	`conf`	4.1 22nm Next-generation IBM System z microprocessor. ISSCC James D. Warnock, Brian W. Curran, John Badar, Gregory Fredeman, Donald W. Plass, Yuen H. Chan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Frank Malgioglio, Guenter Mayer, Christopher J. Berry, Michael H. Wood, Yiu-Hing Chan, Mark D. Mayo, John Isakson, Charudhattan Nagarajan, Tobias Werner, Leon J. Sigal, Ricardo Nigaglioni, Mark Cichanowski, Jeffrey A. Zitz, Matthew M. Ziegler, Tim Bronson, Gerald Strevig, Daniel Dreps, Ruchir Puri, Douglas Malone, Dieter F. Wendel, Pak-kin Mak, Michael A. Blake
2015	—	`conf`	A case study of electromigration reliability: From design point to system operations. IRPS Baozhen Li, K. Paul Muller, James D. Warnock, Leon J. Sigal, Dinesh Badami
2015	J	`jnl`	IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
2015	J	`jnl`	IBM z13 circuit design and methodology. IBM J. Res. Dev. James D. Warnock, Christopher J. Berry, Michael H. Wood, Leon J. Sigal, Yun-Chan Myung, Guenter Mayer, Mark D. Mayo, Y. Chan, Frank Malgioglio, Gerald Strevig, Charudhattan Nagarajan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Howard H. Smith, Di Phan, Ricardo Nigaglioni, Thomas Strach, Matthew M. Ziegler, Niels Fricke, K. Lind, José Neves, Sridhar H. Rangarajan, J. P. Surprise, John Isakson, John Badar, Doug Malone, Donald W. Plass, A. Aipperspach, Dieter F. Wendel, Robert M. Averill III, Ruchir Puri
2015	J	`jnl`	The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban
2014	J	`jnl`	Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module. IEEE J. Solid State Circuits James D. Warnock, Yuen H. Chan, Hubert Harrer, Sean M. Carey, Gerard Salem, Doug Malone, Ruchir Puri, Jeffrey A. Zitz, Adam Jatkowski, Gerald Strevig, Ayan Datta, Anne Gattiker, Aditya Bansal, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, David L. Rude, Leon J. Sigal, Thomas Strach, Howard H. Smith, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb
2013	—	`conf`	5.5GHz system z microprocessor and multi-chip module. ISSCC James D. Warnock, Yuen H. Chan, Hubert Harrer, David L. Rude, Ruchir Puri, Sean M. Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, Adam Jatkowski, Gerald Strevig, Leon J. Sigal, Ayan Datta, Anne Gattiker, Aditya Bansal, Doug Malone, Thomas Strach, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb
2013	—	`conf`	Circuit and PD challenges at the 14nm technology node. ISPD James D. Warnock
2012	J	`jnl`	Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. IEEE J. Solid State Circuits James D. Warnock, Yiu-Hing Chan, Sean M. Carey, Huajun Wen, Patrick J. Meaney, Guenter Gerwig, Howard H. Smith, Yuen H. Chan, John Davis, Paul Bunce, Antonio Pelella, Daniel Rodko, Pradip Patel, Thomas Strach, Doug Malone, Frank Malgioglio, José Neves, David L. Rude, William V. Huott
2011	—	`conf`	A 5.2GHz microprocessor chip for the IBM zEnterprise™ system. ISSCC James D. Warnock, Y. Chan, William V. Huott, Sean M. Carey, Michael F. Fee, Huajun Wen, Mary Jo Saccamango, Frank Malgioglio, Patrick J. Meaney, Donald W. Plass, Yuen H. Chan, Mark D. Mayo, Guenter Mayer, Leon J. Sigal, David L. Rude, Robert M. Averill III, Michael H. Wood, Thomas Strach, Howard H. Smith, Brian W. Curran, Eric M. Schwarz, Lee Eisen, Doug Malone, Steve Weitzel, Pak-kin Mak, Thomas J. McPherson, Charles F. Webb
2011	A*	`conf`	Circuit design challenges at the 14nm technology node. DAC James D. Warnock
2011	A*	`conf`	Design, CAD and technology challenges for future processors: 3D perspectives. DAC Jeff Burns, Gary Carpenter, Eren Kursun, Ruchir Puri, James D. Warnock, Michael Scheuermann
2011	J	`jnl`	POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. IEEE J. Solid State Circuits Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban
2011	J	`jnl`	The zEnterprise 196 System and Microprocessor. IEEE Micro Brian W. Curran, Lee Eisen, Eric M. Schwarz, Pak-kin Mak, James D. Warnock, Patrick J. Meaney, Michael F. Fee
2010	—	`conf`	POWER7 ISSCC James D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski
2009	A	`conf`	An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. ICCAD Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif
2007	J	`jnl`	Cell Broadband Engine processor: Design and implementation. IBM J. Res. Dev. Mack W. Riley, James D. Warnock, Dieter F. Wendel
2007	J	`jnl`	Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits James D. Warnock, William Bidermann, Albert van der Werf, Katsuyuki Sato
2006	J	`jnl`	Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor. IEEE J. Solid State Circuits James D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jürgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen
2006	—	`conf`	Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. ASP-DAC Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel
2006	J	`jnl`	Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. IEEE J. Solid State Circuits Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa
2005	J	`jnl`	Cell Processor Low-Power Design Methodology. IEEE Micro Daniel L. Stasiak, Rajat Chaudhry, Dennis Cox, Stephen D. Posluszny, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Michael Wang
2005	—	`conf`	The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. CICC Dac C. Pham, Erwin Behnen, Mark Bolliger, H. Peter Hofstee, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Yoshio Masubuchi, Stephen D. Posluszny, Mack W. Riley, Masakazu Suzuoki, Michael Wang, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Kazuaki Yazawa
2002	J	`jnl`	The circuit and physical design of the POWER4 microprocessor. IBM J. Res. Dev. James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip J. Restle, Brian A. Zoric, Carl J. Anderson
1997	J	`jnl`	A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. IEEE J. Solid State Circuits Charles F. Webb, Carl J. Anderson, Leon J. Sigal, Kenneth L. Shepard, John S. Liptay, James D. Warnock, Brian W. Curran, Barry Krumm, Mark D. Mayo, Peter J. Camporese, Eric M. Schwarz, Mark S. Farrell, Phillip J. Restle, Robert M. Averill III, Timothy J. Slegel, William V. Huott, Yuen H. Chan, Bruce Wile, Thao N. Nguyen, Philip G. Emma, Daniel K. Beece, Ching-Te Chuang, Cyril Price
1997	J	`jnl`	Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. IBM J. Res. Dev. Leon J. Sigal, James D. Warnock, Brian W. Curran, Yuen H. Chan, Peter J. Camporese, Mark D. Mayo, William V. Huott, Daniel R. Knebel, Ching-Te Chuang, James P. Eckhardt, Philip T. Wu
1997	C	`conf`	High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor. ICCD James D. Warnock, Leon J. Sigal, Brian W. Curran, Yuen H. Chan
1995	J	`jnl`	CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications. IBM J. Res. Dev. Ghavam G. Shahidi, James D. Warnock, James Comfort, Stephen E. Fischer, Patricia A. McFarland, Alexandre Acovic, Terry I. Chappell, Barbara A. Chappell, Tak H. Ning, Carl J. Anderson, Robert H. Dennard, Jack Y.-C. Sun, Michael R. Polcari, Bijan Davari
1992	J	`jnl`	12.8-ps 1.0-mW charge-buffered active pull-down NTL circuit. IEEE J. Solid State Circuits Kenneth Chin, Ching-Te Chuang, James D. Warnock
1992	J	`jnl`	Multigigahertz voltage-controlled oscillators in advanced silicon bipolar technology. IEEE J. Solid State Circuits Mehmet Soyuer, James D. Warnock
1989	J	`jnl`	A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage. IEEE J. Solid State Circuits Kai-Yap Toh, Ching-Te Chuang, Tze-Chiang Chen, James D. Warnock