James D. Meindl

63 papers A* 2A 10C 3Journal 28Unranked 20

Year	Rank	Type	Title / Venue / Authors
2010	—	`conf`	Nanoelectronics in retrospect, prospect and principle. ISSCC James D. Meindl, Azad Naeemi, Muhannad S. Bakir, R. Murali
2008	—	`conf`	3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation. CICC Muhannad S. Bakir, Calvin King, Deepak C. Sekar, Hiren D. Thacker, Bing Dang, Gang Huang, Azad Naeemi, James D. Meindl
2008	J	`jnl`	Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method. IEEE Trans. Very Large Scale Integr. Syst. Kaveh Shakeri, James D. Meindl
2008	A	`conf`	Physical models for electron transport in graphene nanoribbons and their junctions. ICCAD Azad Naeemi, James D. Meindl
2007	—	`conf`	Carbon nanotube interconnects. ISPD Azad Naeemi, James D. Meindl
2007	A	`conf`	IntSim: A CAD tool for optimization of multilevel interconnect networks. ICCAD Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl
2007	A*	`conf`	Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. DAC Azad Naeemi, Reza Sarvari, James D. Meindl
2007	—	`conf`	Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots. CICC Gang Huang, Deepak C. Sekar, Azad Naeemi, Kaveh Shakeri, James D. Meindl
2007	—	`conf`	Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems. CICC Muhannad S. Bakir, Bing Dang, James D. Meindl
2006	A	`conf`	Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects. ITC Hiren D. Thacker, James D. Meindl
2004	—	`conf`	Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution. SoCC Kaveh Shakeri, Muhannad S. Bakir, James D. Meindl
2004	J	`jnl`	Global interconnect design in a three-dimensional system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. James W. Joyner, Payman Zarkesh-Ha, James D. Meindl
2004	—	`conf`	Relative inductance extraction method. CICC Kaveh Shakeri, James D. Meindl
2003	J	`jnl`	Beyond Moore's Law: the interconnect era. Comput. Sci. Eng. James D. Meindl
2003	J	`jnl`	Interconnect Opportunities for Gigascale Integration. IEEE Micro James D. Meindl
2003	J	`jnl`	Modeling technology impact on cluster microprocessor performance. IEEE Trans. Very Large Scale Integr. Syst. Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills
2002	—	`conf`	A compact delay model for series-connected MOSFETs. ACM Great Lakes Symposium on VLSI Kaveh Shakeri, James D. Meindl
2002	A*	`conf`	A physical model for the transient response of capacitively loaded distributed rlc interconnects. DAC Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl
2002	J	`jnl`	Electrical and optical clock distribution networks for gigascale microprocessors. IEEE Trans. Very Large Scale Integr. Syst. A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl
2002	J	`jnl`	Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE J. Solid State Circuits Keith A. Bowman, Steven G. Duvall, James D. Meindl
2002	J	`jnl`	Interconnect opportunities for gigascale integration. IBM J. Res. Dev. James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl
2002	—	`conf`	Low-power circuit advantages of the scaled accumulation FET. ISCAS (5) R. Murali, Lihui Wang, Blanca Austin, James D. Meindl
2002	—	`conf`	Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection. CICC Muhannad S. Bakir, Hollie A. Reed, Anthony V. Mulé, Paul A. Kohl, Kevin P. Martin, James D. Meindl
2002	—	`conf`	Temperature Variable Supply Voltage for Power Reduction. ISVLSI Kaveh Shakeri, James D. Meindl
2001	J	`jnl`	Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. IEEE Trans. Computers Lucian Codrescu, D. Scott Wills, James D. Meindl
2001	J	`jnl`	Impact of three-dimensional architectures on interconnects in gigascale integration. IEEE Trans. Very Large Scale Integr. Syst. James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
2001	—	`conf`	Impact of within-die parameter fluctuations on future maximum clock frequency distributions. CICC Keith A. Bowman, James D. Meindl
2001	J	`jnl`	Interconnect limits on gigascale integration (GSI) in the 21st century. Proc. IEEE Jeffery A. Davis, Raguraman Venkatesan, Alan Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, James D. Meindl
2001	C	`conf`	Interconnect-centric Array Architectures for Minimum SRAM Access Time. ICCD Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl
2001	C	`conf`	On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. ICCD Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl
2001	J	`jnl`	Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). IEEE Trans. Very Large Scale Integr. Syst. Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
2001	J	`jnl`	Special issue on limits of semiconductor technology. Proc. IEEE James D. Meindl
2001	J	`jnl`	The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid State Circuits Azeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl
2000	J	`jnl`	A compact physical via blockage model. IEEE Trans. Very Large Scale Integr. Syst. Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl
2000	J	`jnl`	A minimum total power methodology for projecting limits on CMOS GSI. IEEE Trans. Very Large Scale Integr. Syst. Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl
2000	—	`conf`	CMOS system-on-a-chip voltage scaling beyond 50nm. ACM Great Lakes Symposium on VLSI Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl
2000	—	`conf`	Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). SLIP Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl
2000	J	`jnl`	Heterogeneous architecture models for interconnect-motivated system design. IEEE Trans. Very Large Scale Integr. Syst. Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl
2000	A	`conf`	Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. ISLPED Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
2000	—	`conf`	Prediction of interconnect fan-out distribution using Rent's rule. SLIP Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl
2000	J	`jnl`	Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
2000	J	`jnl`	The fundamental limit on binary switching energy for terascale integration (TSI). IEEE J. Solid State Circuits James D. Meindl, Jeffrey A. Davis
2000	—	`conf`	Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. SLIP James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
1999	J	`jnl`	A physical alpha-power law MOSFET model. IEEE J. Solid State Circuits Keith A. Bowman, Blanca Austin, John C. Eble, Xinghai Tang, James D. Meindl
1999	—	`conf`	Characterization and modeling of clock skew with process variations. CICC Payman Zarkesh-Ha, Tony Mule, James D. Meindl
1999	—	`conf`	Exploring Microprocessor Architectures for Gigascale Integration. ARVLSI Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl
1999	—	`conf`	XXI Century Gigascale Integration (GSI) : The Interconnect Problem. ARVLSI James D. Meindl
1998	A	`conf`	Minimum supply voltage for bulk Si CMOS GSI. ISLPED Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl
1998	—	`conf`	On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule. CICC Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl
1997	A	`conf`	A history of low power electronics: how it began and where it's headed. ISLPED James D. Meindl
1997	J	`jnl`	Intrinsic MOSFET parameter fluctuations due to random dopant placement. IEEE Trans. Very Large Scale Integr. Syst. Xinghai Tang, Vivek De, James D. Meindl
1996	A	`conf`	A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). ISLPED Vivek De, James D. Meindl
1996	A	`conf`	Circuit techniques for low-power CMOS GSI. ISLPED Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl
1996	A	`conf`	Effects of random MOSFET parameter fluctuations on total power consumption. ISLPED Xinghai Tang, Vivek De, James D. Meindl
1995	J	`jnl`	Low power microelectronics: retrospect and prospect. Proc. IEEE James D. Meindl
1994	J	`jnl`	Short channel models and scaling limits of SOI and bulk MOSFETs. IEEE J. Solid State Circuits Bhavna Agrawal, Vivek K. De, Joseph M. Pimbley, James D. Meindl
1993	J	`jnl`	An analytical threshold voltage and subthreshold current model for short-channel AlGaAs/GaAs MODFETs. IEEE J. Solid State Circuits Vivek K. De, James D. Meindl
1993	J	`jnl`	An analytical threshold voltage and subthreshold current model for short-channel MESFETs. IEEE J. Solid State Circuits Vivek K. De, James D. Meindl
1993	J	`jnl`	Analytical drain current models for AlGaAs/GaAs MODFET's including subthreshold conduction. IEEE J. Solid State Circuits Vivek K. De, James D. Meindl
1991	C	`conf`	Design and Test Automation-Gigascale Integration (GSI) in the 21st Century. ICCD James D. Meindl
1991	A	`conf`	Gigascale integration (GSI) technology. SC James D. Meindl
1988	J	`jnl`	Offset word-line architecture for scaling DRAMs to the gigabit level. IEEE J. Solid State Circuits Roy E. Scheuerlein, James D. Meindl
1986	J	`jnl`	Scanning the issue. Proc. IEEE Kenneth A. Pickar, James D. Meindl