James Coole

11 papers A* 1Misc 4Journal 4Unranked 2
YearRankTypeTitle / Venue / Authors
2018 — conf
A Recurrently Generated Overlay Architecture for Rapid FPGA Application Development.
HEART
David Wilson, Greg Stitt, James Coole
2017 A* conf
Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs.
DAC
Anshuman Verma, Huiyang Zhou, Skip Booth, Robbie King, James Coole, Andy Keep, John Marshall, Wu-chun Feng
2015 Misc conf
Adjustable-Cost Overlays for Runtime Compilation.
FCCM
James Coole, Greg Stitt
2014 J jnl
Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts.
IEEE Micro
James Coole, Greg Stitt
2012 Misc conf
BPR: fast FPGA placement and routing using macroblocks.
CODES+ISSS
James Coole, Greg Stitt
2011 J jnl
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing.
IEEE Des. Test Comput.
Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole
2011 J jnl
Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation.
IEEE Embed. Syst. Lett.
Greg Stitt, James Coole
2010 Misc conf
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing.
CODES+ISSS
James Coole, Greg Stitt
2010 J jnl
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures.
Int. J. Reconfigurable Comput.
James Coole, Greg Stitt
2009 — conf
A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation.
ReConFig
James Coole, John Robert Wernsing, Greg Stitt
2008 Misc conf
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures.
CODES+ISSS
Greg Stitt, Gaurav Chaudhari, James Coole