James Chien-Mo Li

85 papers A* 5A 19B 2Misc 5Journal 29Unranked 25

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Automatic IR-Informed Timing and Timing-Aware IR Optimization. ITC-Asia Po-Chieh Yen, Wei-Shen Wang, Shao-Yu Wu, Bing-Chen Li, James Chien-Mo Li, Norman Chang, Ying-Shiun Li, Lang Lin, Akhilesh Kumar
2025	A	`conf`	Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up. ITC Min-Hsin Liu, Ding-Wei Cheng, James Chien-Mo Li, Chris Nigh, Szu Huat Goh, Mason Chern, Bing-Han Hsieh, Subhadip Kundu
2025	—	`conf`	Efficient ML-Based Transient Thermal Prediction for 3D-ICs. ASP-DAC Yun-Feng Yang, Wei-Shen Wang, Yung-Jen Lee, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li, Jessica Yen, Lang Lin
2025	—	`conf`	Fault-Detecting Randomized Benchmarking for Testing Quantum Processors. ITC-Asia Cynthia Kuan, Cheng-Yun Hsieh, Shan-Chi Shih, James Chien-Mo Li
2025	Misc	`conf`	ML-based Adaptive Wafer Sort to Preserve Diagnostic Information. VTS Yun-Sheng Liu, Min-Hsin Liu, James Chien-Mo Li
2025	Misc	`conf`	Multi-core Vmin and Worst-core Vmin Prediction using SOMAC. VTS Jeng-Yu Liao, Li-Yang Wang, James Chien-Mo Li, Harry H. Chen
2024	A*	`conf`	Low-Complexity Algorithmic Test Generation for Neuromorphic Chips. DAC Hsu-Yu Huang, Chu-Yun Hsiao, Tsung-Te Liu, James Chien-Mo Li
2024	J	`jnl`	Small Sampling Overhead Error Mitigation for Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cheng-Yun Hsieh, Hsin-Ying Tsai, Yuan-Hsiang Lu, James Chien-Mo Li
2024	B	`conf`	Test Compression for Neuromorphic Chips. ETS Xin-Ping Chen, Hsu-Yu Huang, Chu-Yun Hsiao, Jennifer Shueh-Inn Hu, James Chien-Mo Li
2024	—	`conf`	Thermal-Aware Test Frequency Optimization. ITC-Asia Wei-Shen Wang, Zhe-Jia Liang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li
2024	A	`conf`	qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors. ITC Yen-Wei Li, Cheng-Yun Hsieh, Meng-Chen Wu, James Chien-Mo Li
2023	Misc	`conf`	Diagnosis of Quantum Circuits in the NISQ Era. VTS Yu-Min Li, Cheng-Yun Hsieh, Yen-Wei Li, James Chien-Mo Li
2023	A	`conf`	Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis. ITC Bing-Han Hsieh, Yun-Sheng Liu, James Chien-Mo Li, Chris Nigh, Mason Chern, Gaurav Bhargava
2023	A	`conf`	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns. ITC Zhe-Jia Liang, Yu-Tsung Wu, Yun-Feng Yang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li
2023	Misc	`conf`	Vmin Prediction Using Nondestructive Stress Test. VTS Chun Chen, Jeng-Yu Liao, James Chien-Mo Li, Harry H. Chen, Eric Jia-Wei Fang
2022	A	`conf`	Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips. ICCAD I-Wei Chiu, Xin-Ping Chen, Jennifer Shueh-Inn Hu, James Chien-Mo Li
2022	A	`conf`	Diagnosing Double Faulty Chains through Failing Bit Separation. ITC Cheng-Sian Kuo, Bing-Han Hsieh, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava, Mason Chern
2022	A	`conf`	ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption. ITC Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh
2021	—	`conf`	Fault Modeling and Testing of Spiking Neural Network Chips. ITC-Asia Yi-Zhan Hsieh, Hsiao-Yin Tseng, I-Wei Chiu, James Chien-Mo Li
2021	A	`conf`	Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization. ITC Mu-Ting Wu, Cheng-Sian Kuo, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava
2021	A	`conf`	Machine Learning-Based Test Pattern Generation for Neuromorphic Chips. ICCAD Hsiao-Yin Tseng, I-Wei Chiu, Mu-Ting Wu, James Chien-Mo Li
2021	A	`conf`	Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning. ITC Yen-Ting Kuo, Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh
2020	—	`conf`	Diagnosis technique for Clustered Multiple Transition Delay Faults. ITC-Asia Yan-Shen You, Chih-Yan Liu, Mu-Ting Wu, Po-Wei Chen, James Chien-Mo Li
2020	—	`conf`	High Efficiency and Low Overkill Testing for Probabilistic Circuits. ITC-Asia Ming-Ting Lee, Chen-Hung Wu, Shi-Tang Liu, Cheng-Yun Hsieh, James Chien-Mo Li
2020	A*	`conf`	Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits. DAC Cheng-Yun Hsieh, Chen-Hung Wu, Chia-Hsien Huang, His-Sheng Goan, James Chien-Mo Li
2020	—	`conf`	Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips. ATS Chih-Yan Liu, Mu-Ting Wu, James Chien-Mo Li, Gaurav Bhargava, Chris Nigh
2020	A	`conf`	qATG: Automatic Test Generation for Quantum Circuits. ITC Chen-Hung Wu, Cheng-Yun Hsieh, Jiun-Yun Li, James Chien-Mo Li
2019	—	`conf`	ATPG and Test Compression for Probabilistic Circuits. VLSI-DAT Kai-Chieh Yang, Ming-Ting Lee, Chen-Hung Wu, James Chien-Mo Li
2019	J	`jnl`	DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li
2018	J	`jnl`	A new method for parameter estimation of high-order polynomial-phase signals. Signal Process. Runqing Cao, James Chien-Mo Li, Lei Zuo, Zeyu Wang, Yunlong Lu
2018	—	`conf`	Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations. VLSI-DAT Yu-Ching Li, Shih-Yao Lin, Heng-Yi Lin, James Chien-Mo Li
2018	A*	`conf`	Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. DAC Run-Yi Wang, Chia-Cheng Pai, Junjie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang
2018	—	`conf`	Parallel order ATPG for test compaction. VLSI-DAT Yu-Wei Chen, Yu-Hao Ho, Chih-Ming Chang, Kai-Chieh Yang, Ming-Ting Li, James Chien-Mo Li
2018	A	`conf`	Test methodology for PCHB/PCFB Asynchronous Circuits. ITC Ting-Yu Shen, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li, Samuel Pan
2017	J	`jnl`	PSN-aware circuit test timing prediction using machine learning. IET Comput. Digit. Tech. Yu-Cheng Liu, Cheng-Yu Han, Shih-Ya Lin, James Chien-Mo Li
2017	—	`conf`	Physical-aware diagnosis of multiple interconnect defects. ITC-Asia Po-Hao Chen, Chi-Lin Lee, Jing-Yu Chen, Po-Wei Chen, James Chien-Mo Li
2017	—	`conf`	Robust test pattern generation for hold-time faults in nanometer technologies. VLSI-DAT Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang, James Chien-Mo Li
2017	—	`conf`	Test Pattern Compression for Probabilistic Circuits. ATS Chih-Ming Chang, Kai-Jie Yang, James Chien-Mo Li, Hung Chen
2016	J	`jnl`	A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hung-I Lee, Chen-Yo Han, James Chien-Mo Li
2016	J	`jnl`	Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Cheng-Yu Han, Yu-Ching Li, Hao-Tien Kan, James Chien-Mo Li
2016	J	`jnl`	Test Pattern Modification for Average IR-Drop Reduction. IEEE Trans. Very Large Scale Integr. Syst. Wei-Sheng Ding, Hung-Yi Hsieh, Cheng-Yu Han, James Chien-Mo Li, Xiaoqing Wen
2015	—	`conf`	Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. ATS Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li
2015	—	`conf`	TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects. VLSI-DAT Ang-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, James Chien-Mo Li
2014	A	`conf`	Divide and conquer diagnosis for multiple defects. ITC Shih-Min Chao, Po-Juei Chen, Jing-Yu Chen, Po-Hao Chen, Ang-Feng Lin, James Chien-Mo Li, Pei-Ying Hsueh, Chun-Yi Kuo, Ying-Yen Chen, Jih-Nung Li
2014	B	`conf`	GPU-based timing-aware test generation for small delay defects. ETS Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, James Chien-Mo Li, Michael S. Hsiao, Laung-Terng Wang
2014	J	`jnl`	Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li
2014	J	`jnl`	Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. Chun-Yi Kuo, Chi-Jih Shih, Yi-Chang Lu, James Chien-Mo Li, Krishnendu Chakrabarty
2014	J	`jnl`	Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk. IEEE Trans. Very Large Scale Integr. Syst. Ming-Hong Tsai, Wei-Sheng Ding, Hung-Yi Hsieh, James Chien-Mo Li
2013	—	`conf`	Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. Asian Test Symposium Bing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li
2013	J	`jnl`	Compact Test Pattern Selection for Small Delay Defect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chia-Yuan Chang, Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li, Jiann-Chyi Rau
2013	A*	`conf`	GPU-based n-detect transition fault ATPG. DAC Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li
2013	—	`conf`	Test Generation of Path Delay Faults Induced by Defects in Power TSV. Asian Test Symposium Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, Krishnendu Chakrabarty
2012	—	`conf`	3D IC test scheduling using simulated annealing. VLSI-DAT Chih-Yao Hsu, Chun-Yi Kuo, James Chien-Mo Li, Krishnendu Chakrabarty
2012	J	`jnl`	A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores. IEEE Trans. Very Large Scale Integr. Syst. Geng-Ming Chiu, James Chien-Mo Li
2012	J	`jnl`	An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. IEEE Trans. Circuits Syst. I Regul. Pap. Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen
2012	J	`jnl`	Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang
2012	J	`jnl`	Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis. IEEE Trans. Computers Wei-Lin Tsai, Wei-Chih Liu, James Chien-Mo Li
2011	J	`jnl`	A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kuan-Yu Liao, Chia-Yuan Chang, James Chien-Mo Li
2011	—	`conf`	An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects. Asian Test Symposium Po-Juei Chen, Wei-Li Hsu, James Chien-Mo Li, Nan-Hsin Tseng, Kuo-Yin Chen, Wei-pin Changchien, Charles C. C. Liu
2011	J	`jnl`	An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology. J. Electron. Test. Chi-Hsuan Cheng, James Chien-Mo Li
2011	—	`conf`	An at-speed self-testable technique for the high speed domino adder. CICC Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen
2011	J	`jnl`	Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. IET Comput. Digit. Tech. W.-C. Wang, C.-Y. Hsu, James Chien-Mo Li, Y.-C. Sung, A. Rao, L.-T. Wang
2011	A	`conf`	Test clock domain optimization for peak power supply noise reduction during scan. ITC Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li
2011	J	`jnl`	Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu
2010	Misc	`conf`	CSER: BISER-based concurrent soft-error resilience. VTS Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li
2010	A*	`conf`	Static timing analysis for flexible TFT circuits. DAC Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li
2009	A	`conf`	BIST design optimization for large-scale embedded memory cores. ICCAD Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng
2009	—	`conf`	Bridging Fault Diagnosis to Identify the Layer of Systematic Defects. Asian Test Symposium Po-Juei Chen, James Chien-Mo Li, Hsing Jasmine Chao
2009	J	`jnl`	Time-space test response compaction and diagnosis based on BCH codes. IET Comput. Digit. Tech. F.-M. Wang, W.-C. Wang, James Chien-Mo Li
2009	—	`conf`	Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits. Asian Test Symposium Shiue-Tsung Shen, Wei-Hsiao Liu, En-Hua Ma, James Chien-Mo Li, I-Chun Cheng
2008	J	`jnl`	A Two-level Simultaneous Test Data and Time Reduction Technique for SOC. J. Inf. Sci. Eng. Yu-Te Liaw, Bing-Chuan Bai, James Chien-Mo Li
2008	A	`conf`	Diagnosis of Logic-to-chain Bridging Faults. ITC Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin, James Chien-Mo Li
2008	J	`jnl`	Diagnosis of Multiple Scan Chain Timing Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li
2008	J	`jnl`	Effective and Economic Phase Noise Testing for Single-Chip TV Tuners. IEEE Trans. Instrum. Meas. James Chien-Mo Li, Po-Chou Lin, Chih-Ming Chiang, Chuo-Jan Pan, Chao-Wen Tseng
2008	A	`conf`	IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores. ITC Geng-Ming Chiu, James Chien-Mo Li
2008	—	`conf`	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte
2008	J	`jnl`	Survey of Scan Chain Diagnosis. IEEE Des. Test Comput. Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li
2007	J	`jnl`	Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis. IEEE Trans. Computers James Chien-Mo Li, Hung-Mao Lin, Fang-Min Wang
2007	—	`conf`	Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies. ASP-DAC Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li
2007	J	`jnl`	Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing. J. Low Power Electron. Chun-Yi Lee, James Chien-Mo Li
2006	A	`conf`	Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis. ITC Yu-Long Kao, Wei-Shun Chuang, James Chien-Mo Li
2005	A	`conf`	Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains. ITC Hung-Mao Lin, James Chien-Mo Li
2005	J	`jnl`	Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains. IEEE Trans. Computers James Chien-Mo Li
2005	J	`jnl`	Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. James Chien-Mo Li
2005	J	`jnl`	Diagnosis of single stuck-at faults and multiple timing faults in scan chains. IEEE Trans. Very Large Scale Integr. Syst. James Chien-Mo Li