James C. Hoe - RankMe

129 papers A* 21A 24B 9C 8Misc 9Journal 32Unranked 23

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Analysis and Optimization of Input-Dependent Stream Processing Pipelines on FPGAs. FPGA Shashank Obla, Bin Li, James C. Hoe
2025	—	`conf`	A RISC-V Vector Extension for Multi-word Arithmetic. SC Workshops Yunhao Lan, Larry Tang, Naifeng Zhang, Youngjin Eum, James C. Hoe, Franz Franchetti
2025	J	`jnl`	Derek Chiou. IEEE Micro Doug Burger, Paul Chow, Joel S. Emer, Mark D. Hill, James C. Hoe, Masato Motomura
2025	—	`conf`	HLS to FPGAs: Extending Software Regions Via Transformations and Offloading Functions to the CPU. MCSoC Tiago Santos, João Bispo, João M. P. Cardoso, James C. Hoe
2025	—	`conf`	Hardware-Software Co-Design of Iterative Filter-Update Numerical Methods Using Processing-In-Memory. SC Workshops Eric Tang, Tianyun Zhang, William Bradford, Farzana Ahmed Siddique, James C. Hoe, Kevin Skadron, Franz Franchetti
2025	Misc	`conf`	On Improving the HLS Compatibility of Large C/C++ Code Regions. FCCM Tiago Santos, João Bispo, João M. P. Cardoso, James C. Hoe
2025	A*	`conf`	Reconfigurable Stream Network Architecture. ISCA Chengyue Wang, Xiaofan Zhang, Jason Cong, James C. Hoe
2024	J	`jnl`	Addressing Architectural Obstacles for Overlay with Stream Network Abstraction. CoRR Chengyue Wang, Xiaofan Zhang, Jason Cong, James C. Hoe
2023	A*	`conf`	Ensō: A Streaming Interface for NIC-Application Communication. OSDI Hugo Sadok, Nirav Atre, Zhipeng Zhao, Daniel S. Berger, James C. Hoe, Aurojit Panda, Justine Sherry, Ren Wang
2023	J	`jnl`	Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA. IEEE Trans. Computers Zhipeng Zhao, Joseph Melber, Siddharth Sahay, Shashank Obla, Eriko Nurvitadhi, James C. Hoe
2023	J	`jnl`	Perspectives on AI Architectures and Co-design for Earth System Predictability. CoRR Maruti K. Mudunuru, James A. Ang, Mahantesh Halappanavar, Simon D. Hammond, Maya B. Gokhale, James C. Hoe, Tushar Krishna, Sarat Sreepathi, Matthew R. Norman, Ivy Bo Peng, Philip W. Jones
2022	—	`conf`	Flexible Hardware Accelerator Design Generation with Spiral. HPEC Guanglin Xu, James C. Hoe, Franz Franchetti
2022	—	`conf`	Pigasus 2.0: making the pigasus IDS robust to attacks and different workloads. SIGCOMM Posters and Demos Zhipeng Zhao, Nirav Atre, Hugo Sadok, Siddharth Sahay, Shashank Obla, James C. Hoe, Justine Sherry
2021	J	`jnl`	A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem. CoRR Daehyeok Kim, Nikita Lazarev, Tommy Tracy II, Farzana Siddique, Hun Namkung, James C. Hoe, Vyas Sekar, Kevin Skadron, Zhiru Zhang, Srinivasan Seshan
2021	A*	`conf`	HerQules: securing programs via hardware-enforced message queues. ASPLOS Daming D. Chen, Wen Shih Lim, Mohammad Bakhshalipour, Phillip B. Gibbons, James C. Hoe, Bryan Parno
2021	A	`conf`	We need kernel interposition over the network dataplane. HotOS Hugo Sadok, Zhipeng Zhao, Valerie Choung, Nirav Atre, Daniel S. Berger, James C. Hoe, Aurojit Panda, Justine Sherry
2020	B	`conf`	A Service-Oriented Memory Architecture for FPGA Computing. FPL Joseph Melber, James C. Hoe
2020	A*	`conf`	Achieving 100Gbps Intrusion Prevention on a Single Server. OSDI Zhipeng Zhao, Hugo Sadok, Nirav Atre, James C. Hoe, Vyas Sekar, Justine Sherry
2020	—	`conf`	Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs. FPT Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, Martin Langhammer
2020	J	`jnl`	High-Performance Memory Snapshotting for Real-Time, Consistent, Hypervisor-Based Monitors. IEEE Trans. Dependable Secur. Comput. Peter F. Klemperer, Hye Yoon Jeon, Bryan D. Payne, James C. Hoe
2020	B	`conf`	Partial Reconfiguration for Design Optimization. FPL Marie Nguyen, Nathan Serafin, James C. Hoe
2020	J	`jnl`	Partial Reconfiguration for Design Optimization. CoRR Marie Nguyen, Nathan Serafin, James C. Hoe
2019	A*	`conf`	Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization. MICRO Fazle Sadi, Joe Sweeney, Tze Meng Low, James C. Hoe, Larry T. Pileggi, Franz Franchetti
2019	Misc	`conf`	Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform. FCCM Yu Wang, James C. Hoe, Eriko Nurvitadhi
2019	B	`conf`	Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision Applications. FPL Marie Nguyen, Robert Tamburo, Srinivasa G. Narasimhan, James C. Hoe
2018	—	`conf`	PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV. HPEC Fazle Sadi, Joe Sweeney, Scott McMillan, Tze Meng Low, James C. Hoe, Larry T. Pileggi, Franz Franchetti
2018	J	`jnl`	SPIRAL: Extreme Performance Portability. Proc. IEEE Franz Franchetti, Tze Meng Low, Doru-Thom Popovici, Richard Michael Veras, Daniele G. Spampinato, Jeremy R. Johnson, Markus Püschel, James C. Hoe, José M. F. Moura
2018	B	`conf`	Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration. FPL Marie Nguyen, James C. Hoe
2018	J	`jnl`	Time-Shared Execution of Realtime Streaming Pipelines by Dynamic Partial Reconfiguration. CoRR Marie Nguyen, James C. Hoe
2017	J	`jnl`	Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation. CoRR Marie Nguyen, James C. Hoe
2017	A	`conf`	Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only). FPGA Zhipeng Zhao, James C. Hoe
2017	J	`jnl`	Using Vivado-HLS for Structural Design: a NoC Case Study. CoRR Zhipeng Zhao, James C. Hoe
2016	—	`ch.`	3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. Large-Scale Visual Geo-Localization Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen
2016	A	`conf`	A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems. FPGA Gabriel Weisz, Joseph Melber, Yu Wang, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe
2016	J	`jnl`	FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation. J. Signal Process. Syst. Berkin Akin, Franz Franchetti, James C. Hoe
2016	J	`jnl`	FPGA compute acceleration is first about energy efficiency: technical perspective. Commun. ACM James C. Hoe
2016	J	`jnl`	HAMLeT Architecture for Parallel Data Reorganization in Memory. IEEE Micro Berkin Akin, Franz Franchetti, James C. Hoe
2015	B	`conf`	CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing. FPL Gabriel Weisz, James C. Hoe
2015	B	`conf`	DELPHI: a framework for RTL-based architecture design evaluation using DSENT models. ISPASS Michael Papamichael, Cagla Cakir, Chen Sun, Chia-Hsin Owen Chen, James C. Hoe, Ken Mai, Li-Shiuan Peh, Vladimir Stojanovic
2015	A*	`conf`	Data reorganization in memory using 3D-stacked DRAM. ISCA Berkin Akin, Franz Franchetti, James C. Hoe
2015	A*	`conf`	Enabling portable energy efficiency with memory accelerated library. MICRO Qi Guo, Tze Meng Low, Nikolaos Alachiotis, Berkin Akin, Larry T. Pileggi, James C. Hoe, Franz Franchetti
2015	A*	`conf`	Nautilus: fast automated IP design space search using guided genetic algorithms. DAC Michael K. Papamichael, Peter A. Milder, James C. Hoe
2015	J	`jnl`	The CONNECT Network-on-Chip Generator. Computer Michael K. Papamichael, James C. Hoe
2014	—	`conf`	Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory. HPEC Fazle Sadi, Berkin Akin, Doru-Thom Popovici, James C. Hoe, Larry T. Pileggi, Franz Franchetti
2014	Misc	`conf`	FFTS with near-optimal memory access through block data layouts. ICASSP Berkin Akin, Franz Franchetti, James C. Hoe
2014	—	`book`	FPGA-Accelerated Simulation of Computer Systems Hari Angepat, Derek Chiou, Eric S. Chung, James C. Hoe
2014	Misc	`conf`	GraphGen: An FPGA Framework for Vertex-Centric Graph Computation. FCCM Eriko Nurvitadhi, Gabriel Weisz, Yu Wang, Skand Hurkat, Marie Nguyen, James C. Hoe, José F. Martínez, Carlos Guestrin
2014	—	`conf`	HAMLeT: Hardware accelerated memory layout transform within 3D-stacked DRAM. HPEC Berkin Akin, James C. Hoe, Franz Franchetti
2014	—	`conf`	Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations. ICSAMOS Nicolas Ventroux, Julien Peeters, Tanguy Sassolas, James C. Hoe
2014	—	`conf`	Understanding the design space of DRAM-optimized hardware FFT accelerators. ASAP Berkin Akin, Franz Franchetti, James C. Hoe
2013	—	`conf`	3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. CVPR Workshops Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen
2013	—	`conf`	A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. 3DIC Qiuling Zhu, Berkin Akin, Huseyin Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti
2013	A	`conf`	C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction. FPGA Gabriel Weisz, James C. Hoe
2013	A	`conf`	Cross-platform FPGA accelerator development using CoRAM and CONNECT. FPGA Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe
2012	A	`conf`	Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only). FPGA Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe
2012	A	`conf`	CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs. FPGA Michael Papamichael, James C. Hoe
2012	J	`jnl`	Computer Generation of Hardware for Linear Digital Signal Processing Transforms. ACM Trans. Design Autom. Electr. Syst. Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel
2012	A	`conf`	Highly Efficient Performance Portable Tracking of Evolving Surfaces. IPDPS Wei Yu, Franz Franchetti, James C. Hoe, Tsuhan Chen
2012	Misc	`conf`	Improving fixed-point accuracy of FFT cores in O-OFDM systems. ICASSP Robert Koutsoyannis, Peter A. Milder, Christian R. Berger, Madeleine Glick, James C. Hoe, Markus Püschel
2012	Misc	`conf`	Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes. FCCM Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe
2012	A	`conf`	Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. FPGA Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai
2011	J	`jnl`	Automatic Pipelining From Transactional Datapath Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2011	A	`conf`	CoRAM: an in-fabric memory architecture for FPGA-based computing. FPGA Eric S. Chung, James C. Hoe, Ken Mai
2011	J	`jnl`	Commercial Antivirus Software Effectiveness: An Empirical Study. Computer Orathai Sukwong, Hyong S. Kim, James C. Hoe
2011	—	`conf`	FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations. NOCS Michael Papamichael, James C. Hoe, Onur Mutlu
2011	—	`conf`	Integrating formal verification and high-level processor pipeline synthesis. SASP Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2010	A*	`conf`	Automatic multithreaded pipeline synthesis from transactional datapath specifications. DAC Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam
2010	A	`conf`	Automatic pipelining from transactional datapath specifications. DATE Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2010	B	`conf`	Fast bilateral filtering by adapting block size. ICIP Wei Yu, Franz Franchetti, James C. Hoe, Yao-jen Chang, Tsuhan Chen
2010	Misc	`conf`	Hardware implementation of the discrete fourier transform with non-power-of-two problem size. ICASSP Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel
2010	J	`jnl`	High Performance Stereo Vision Designed for Massively Data Parallel Platforms. IEEE Trans. Circuits Syst. Video Technol. Wei Yu, Tsuhan Chen, Franz Franchetti, James C. Hoe
2010	J	`jnl`	High-Level Design and Validation of the BlueSPARC Multithreaded Processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eric S. Chung, James C. Hoe
2010	A*	`ed.`	Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010 ASPLOS James C. Hoe, Vikram S. Adve
2010	A*	`conf`	Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? MICRO Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai
2010	J	`jnl`	The Future of Architectural Simulation. IEEE Micro James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi
2009	C	`conf`	2009 MEMOCODE Co-Design Contest. MEMOCODE Forrest Brewer, James C. Hoe
2009	A	`conf`	Automatic generation of streaming datapaths for arbitrary fixed permutations. DATE Peter A. Milder, James C. Hoe, Markus Püschel
2009	C	`conf`	Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors. PRDC Brian T. Gold, Babak Falsafi, James C. Hoe
2009	—	`conf`	Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe
2009	C	`conf`	Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation. MEMOCODE Eric S. Chung, James C. Hoe
2009	J	`jnl`	Permuting streaming data using RAMs. J. ACM Markus Püschel, Peter A. Milder, James C. Hoe
2009	J	`jnl`	ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. ACM Trans. Reconfigurable Technol. Syst. Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi
2009	B	`conf`	Real time stereo vision using exponential step cost aggregation on GPU. ICIP Wei Yu, Tsuhan Chen, James C. Hoe
2008	A	`conf`	A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2008	A	`conf`	Domain-specific library generation for parallel software and hardware platforms. IPDPS Franz Franchetti, Yevgen Voronenko, Peter A. Milder, Srinivas Chellappa, Marek R. Telgarsky, Hao Shen, Paolo D'Alberto, Frédéric de Mesmay, James C. Hoe, José M. F. Moura, Markus Püschel
2008	A*	`conf`	Formal datapath representation and manipulation for implementing DSP transforms. DAC Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel
2008	J	`jnl`	MEMOCODE 2006 guest editors' introduction. Des. Autom. Embed. Syst. James C. Hoe, Jens Palsberg
2008	C	`conf`	MEMOCODE 2008 Co-Design Contest. MEMOCODE Patrick Schaumont, Krste Asanovic, James C. Hoe
2007	—	`conf`	FFT Compiler: from math to efficient hardware HLDVT invited short paper. HLDVT Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel
2007	Misc	`conf`	Generating FPGA-Accelerated DFT Libraries. FCCM Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryhaila, Franz Franchetti, James C. Hoe, José M. F. Moura, Markus Püschel, Jeremy R. Johnson
2007	C	`conf`	MEMOCODE 2007 Co-Design Contest. MEMOCODE Forrest Brewer, James C. Hoe
2007	A*	`conf`	Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. MICRO Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe
2007	C	`conf`	PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers. PRDC Jangwoo Kim, Jared C. Smolens, Babak Falsafi, James C. Hoe
2007	A	`conf`	PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. IPDPS Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2007	J	`jnl`	RAMP: Research Accelerator for Multiple Processors. IEEE Micro John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
2007	J	`jnl`	Time-Multiplexed Multiple-Constant Multiplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter Tummeltshammer, James C. Hoe, Markus Püschel
2006	A	`conf`	Fast and accurate resource estimation of automatically generated custom DFT IP cores. FPGA Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel
2006	—	`conf`	Research accelerator for multiple processors. Hot Chips Symposium David A. Patterson, Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan M. Rabaey, John Wawrzynek
2006	A*	`conf`	Reunion: Complexity-Effective Multicore Redundancy. MICRO Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe
2006	J	`jnl`	SimFlex: Statistical Sampling of Computer System Simulation. IEEE Micro Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe
2006	B	`conf`	Simulation sampling with live-points. ISPASS Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe
2006	—	`conf`	Spiral: Joint Runtime and Energy Optimization of Linear Transforms. ICASSP (3) Marek R. Telgarsky, James C. Hoe, José M. F. Moura
2006	A	`conf`	Statistical sampling of microarchitecture simulation. IPDPS Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe
2006	J	`jnl`	Statistical sampling of microarchitecture simulation. ACM Trans. Model. Comput. Simul. Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe
2005	A*	`conf`	Automatic generation of customized discrete fourier transform IPs. DAC Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel
2005	J	`jnl`	TRUSS: A Reliable, Scalable Server Architecture. IEEE Micro Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
2005	A*	`conf`	TurboSMARTS: accurate microarchitecture simulation sampling in minutes. SIGMETRICS Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe
2004	—	`conf`	Automatic cost minimization for multiplierless implementations of discrete signal transforms. ICASSP (5) Adam C. Zelinski, Markus Püschel, Smarahara Misra, James C. Hoe
2004	A	`conf`	Custom-optimized multiplierless implementations of DSP algorithms. ICCAD Markus Püschel, Adam C. Zelinski, James C. Hoe
2004	A*	`conf`	Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures. MICRO Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi
2004	J	`jnl`	Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth. IEEE Micro Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
2004	A*	`conf`	Fingerprinting: bounding soft-error detection latency and bandwidth. ASPLOS Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
2004	C	`conf`	In-System FPGA Prototyping of an Itanium Microarchitecture. ICCD Roland E. Wunderlich, James C. Hoe
2004	A	`conf`	In-system FPGA prototyping of an itanium microarchitecture. FPGA Roland E. Wunderlich, James C. Hoe
2004	A*	`conf`	Multiple constant multiplication by time-multiplexed mapping of addition chains. DAC Peter Tummeltshammer, James C. Hoe, Markus Püschel
2004	J	`jnl`	Operation-centric hardware description and synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. James C. Hoe, Arvind
2004	J	`jnl`	SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. SIGMETRICS Perform. Evaluation Rev. Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch, Roland E. Wunderlich, Shelley Chen, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
2004	C	`conf`	Synchronous extensions to operation centric hardware description languages. MEMOCODE Grace Nordin, James C. Hoe
2003	A	`conf`	High-level modeling and FPGA prototyping of microprocessors. FPGA Joydeep Ray, James C. Hoe
2003	A*	`conf`	SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. ISCA Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe
2003	Misc	`conf`	Superscalar out-of-order demystified in four instructions. WCAE James C. Hoe
2001	A*	`conf`	Dual use of superscalar datapath for transient-fault detection and recovery. MICRO Joydeep Ray, James C. Hoe, Babak Falsafi
2000	—	`—`	Operation-centric hardware description and synthesis. James C. Hoe
2000	A	`conf`	Synthesis of Operation-Centric Hardware Descriptions. ICCAD James C. Hoe, Arvind
1999	A	`conf`	A Personal Supercomputer for Climate Research. SC James C. Hoe, Chris Hill, Alistair Adcroft
1999	—	`conf`	Hardware Synthesis from Term Rewriting Systems. VLSI James C. Hoe, Arvind
1998	A	`conf`	MPI-StarT: Delivering Network Performance to Numerical Applications. SC Parry Husbands, James C. Hoe
1995	—	`conf`	START-NG: Delivering Seamless Parallel Computing. Euro-Par Derek Chiou, Boon Seong Ang, Robert Greiner, Arvind, James C. Hoe, Michael J. Beckerle, James E. Hicks, G. Andrew Boughton
1994	—	`conf`	Network substrate for parallel processing on a workstation cluster. Hot Interconnects James C. Hoe, Andy Boughton