James B. Kuo

31 papers C 7Journal 13Unranked 11
YearRankTypeTitle / Venue / Authors
2014 C conf
Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs.
ISCAS
Gregory J. Y. Lin, Chienbo B. Hsu, James B. Kuo
2014 — conf
MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits.
ISIC
Chen-Bo Hsu, James B. Kuo
2014 — conf
MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit.
ICECS
Chen-Bo Hsu, Young Sik Hong, James B. Kuo
2014 — conf
Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device.
ISIC
D. H. Lung, S. K. Hu, James B. Kuo, D. Chen, Y. J. Chen
2014 — conf
Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS.
MWSCAS
Chen-Bo Hsu, James B. Kuo
2011 — conf
Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique.
PATMOS
Henry X. F. Huang, Steven R. S. Shen, James B. Kuo
2010 J jnl
Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect.
Microelectron. Reliab.
H. J. Hung, James B. Kuo, D. Chen, Chih-Sheng Yeh
2010 C conf
Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications.
ISCAS
Chih-Hsiang Lin, James B. Kuo
2009 — conf
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique.
PATMOS
Chih-Hsiang Lin, James B. Kuo
2007 — conf
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS.
PATMOS
Harry I. A. Chen, Edward K. W. Loo, James B. Kuo, Marek Syrzycki
2005 — conf
Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited.
IWSOC
James B. Kuo
2004 — conf
A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI.
ICECS
Hung-Pin Chen, James B. Kuo
2003 — conf
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI.
ISCAS (5)
P. C. Chen, James B. Kuo
2002 J jnl
A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme.
IEEE J. Solid State Circuits
Perng-Fei Lin, James B. Kuo
2001 J jnl
A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell.
IEEE J. Solid State Circuits
Perng-Fei Lin, James B. Kuo
2001 J jnl
A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques.
IEEE J. Solid State Circuits
S. C. Liu, F. A. Wu, James B. Kuo
2000 C conf
A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability.
ISCAS
Bo-Ting Wang, James B. Kuo
1998 — conf
1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder.
ICECS
J. H. Lou, James B. Kuo
1997 J jnl
A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI.
IEEE J. Solid State Circuits
J. H. Lou, James B. Kuo
1996 J jnl
A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Y. G. Chen, James B. Kuo
1995 J jnl
A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technology.
IEEE J. Solid State Circuits
James B. Kuo, K. W. Su, J. H. Lou, S. S. Chen, C. S. Chiang
1995 J jnl
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit.
IEEE J. Solid State Circuits
James B. Kuo, K. W. Su, J. H. Lou
1994 C conf
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit.
ISCAS
James B. Kuo, K. W. Su, J. H. Lou
1994 C conf
A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI.
ISCAS
James B. Kuo, B. Y. Chen, Mark W. Mao
1993 C conf
A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI.
ISCAS
James B. Kuo, Hung-Pin Chen, H. J. Huang
1993 J jnl
A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit.
IEEE J. Solid State Circuits
James B. Kuo, H. J. Liao, H. P. Chen
1993 C conf
A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique.
ISCAS
Mark W. Mao, B. Y. Chen, James B. Kuo
1992 J jnl
A coded block adaptive neural network system with a radical-partitioned structure for large-volume Chinese characters recognition.
Neural Networks
Mark W. Mao, James B. Kuo
1992 J jnl
An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hwang-Cherng Chow, Wu-Shiung Feng, James B. Kuo
1989 J jnl
Two-dimensional analysis of a merged BiPMOS device.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
James B. Kuo, Geert P. Rosseel, Robert W. Dutton
1989 J jnl
Two-dimensional transient analysis of a collector-up ECL inverter.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
James B. Kuo, Tsen-Shau Yang, Robert W. Dutton, Bruce A. Wooley