Jakub Lojda - RankMe

34 papers A 1B 1C 11Journal 1Unranked 20

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Multi-Partner Project: LoLiPoP-IoT - Design and Simulation of Energy-Efficient Devices for the Internet of Things. DATE Jakub Lojda, Josef Strnadel, Pavel Smrz, Václav Simek
2025	C	`conf`	Portable Simulation Models for Energy Aspects of IoT Devices in the LoLiPoP-IoT Project. DSD Jakub Lojda, Daire Joyce, Pavel Smrz, Shruti Kathuria, Josef Strnadel, Caitlin Quinn, Václav Simek, Patrik Staron
2024	—	`conf`	First Steps Towards Unified Low-Power IoT Design: The "DYNAMIC" Framework. EWDTS Jakub Lojda, Josef Strnadel, Pavel Smrz, Václav Simek
2024	—	`conf`	On SMC-Based Dependability Analysis in LoLiPoP-IoT Project. AISoLA Josef Strnadel, Jakub Lojda, Pavel Smrz, Václav Simek
2024	C	`conf`	The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things. DSD Jakub Lojda, Josef Strnadel, Václav Simek, Pavel Smrz, Mike Hayes, Ralf Popp
2023	—	`conf`	The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller. LASCAS Richard Panek, Jakub Lojda
2021	C	`conf`	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. DSD Jakub Lojda, Richard Panek, Zdenek Kotásek
2021	—	`conf`	Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery. EWDTS Jakub Lojda, Richard Panek, Zdenek Kotásek
2021	C	`conf`	Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. DSD Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2021	—	`conf`	Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. LATS Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020	—	`conf`	Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. EWDTS Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020	C	`conf`	Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. DDECS Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotásek
2020	—	`conf`	Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. LASCAS Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020	C	`conf`	Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. DSD Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020	—	`conf`	Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. VLSI-DAT Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2019	—	`conf`	Detecting hard synapses faults in artificial neural networks. LATS Martin Krcma, Zdenek Kotásek, Jakub Lojda
2019	—	`conf`	Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. LATS Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek
2019	—	`conf`	Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. LATS Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2019	C	`conf`	Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. DSD Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek
2018	—	`conf`	An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot Controller. EWDTS Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek
2018	C	`conf`	Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. DSD Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek
2018	C	`conf`	FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. DSD Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek
2018	—	`conf`	Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. EWDTS Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2018	—	`conf`	Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. EWDTS Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2017	B	`conf`	Comparison of FPNNs models approximation capabilities and FPGA resources utilization. ICCP Martin Krcma, Zdenek Kotásek, Jakub Lojda
2017	—	`conf`	Data types and operations modifications: A practical approach to fault tolerance in HLS. EWDTS Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek, Martin Krcma
2017	J	`jnl`	Functional verification based platform for evaluating fault tolerance properties. Microprocess. Microsystems Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek
2017	—	`conf`	Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation. EWDTS Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2017	C	`conf`	Reliability Analysis and Improvement of FPGA-Based Robot Controller. DSD Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek
2017	—	`conf`	Triple modular redundancy used in field programmable neural networks. EWDTS Martin Krcma, Zdenek Kotásek, Jakub Lojda
2016	—	`conf`	Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs. FPT Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek
2016	—	`conf`	HLS-based fault tolerance approach for SRAM-based FPGAs. FPT Jakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek
2016	—	`conf`	Implementation of fault tolerant techniques into FPNNs. FPT Martin Krcma, Zdenek Kotásek, Jakub Lojda
2016	C	`conf`	Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems. DSD Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek