Jakub Janicki - RankMe

18 papers A 8B 2Journal 4Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Chain Cell-Aware Diagnosis. ITC Szczepan Urban, Jakub Janicki, Piotr Zimnowlodzki, Artur Stelmach, Manish Sharma
2025	—	`conf`	Improving Effect-Cause Diagnosis Performance with Minimal Memory Overhead on Asymmetric Partition Trees (APT). ITC-Asia Wu-Tung Cheng, Szczepan Urban, Manish Sharma, Jakub Janicki
2025	A	`conf`	Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects. ITC Wu-Tung Cheng, Manish Sharma, Artur Stelmach, Jakub Janicki, Preston McWithey, Gaurav Veda, Szczepan Urban, Jayant D'Souza
2024	A	`conf`	Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage. ITC Wu-Tung Cheng, Manish Sharma, Xin Yang, Artur Stelmach, Szczepan Urban, Jakub Janicki, Preston McWithey
2023	A	`conf`	Predicting the Resolution of Scan Diagnosis. ITC Manoj Devendhiran, Jakub Janicki, Szczepan Urban, Manish Sharma, Jayant D'Souza
2022	A	`conf`	Industry Evaluation of Reversible Scan Chain Diagnosis. ITC Soumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson
2020	—	`conf`	Scan Chain Diagnosis-Driven Test Response Compactor. ATS Jakub Janicki, Grzegorz Mrugalski, Artur Stelmach, Szczepan Urban
2019	B	`conf`	Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution. ETS Yu Huang, Jakub Janicki, Szczepan Urban
2015	J	`jnl`	Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	J	`jnl`	Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	—	`conf`	High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. ATS Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
2013	A	`conf`	EDT bandwidth management - Practical scenarios for large SoC designs. ITC Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
2013	J	`jnl`	Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2012	B	`conf`	Bandwidth-aware test compression logic for SoC designs. ETS Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski
2012	J	`jnl`	EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2011	A	`conf`	EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2011	—	`conf`	Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki
2010	A	`conf`	Dynamic channel allocation for higher EDT compression in SoC designs. ITC Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer