Jakob Puchinger

51 papers A 1B 5C 3Journal 30Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
Eur. J. Oper. Res.
Shaohua Yu, Ann Melissa Campbell, Jan Fabian Ehmke, Jakob Puchinger
2026 J jnl
CoRR
Boshuai Zhao, Adam F. Abdin, Jakob Puchinger
2026 J jnl
CoRR
Shaohua Yu, Wenhao Mao, Zigao Wu, Jakob Puchinger
2025 J jnl
CoRR
Tarek Chouaki, Sebastian Hörl, Jakob Puchinger
2025 J jnl
Int. J. Prod. Res.
Shichang Xiao, Pan Peng, Shaohua Yu, Jakob Puchinger
2024 J jnl
Comput. Ind. Eng.
Hongping Wang, Adam F. Abdin, Yi-Ping Fang, Jakob Puchinger, Enrico Zio
2024 J jnl
Eur. J. Oper. Res.
Shaohua Yu, Jakob Puchinger, Shudong Sun
2024 J jnl
Comput. Oper. Res.
Jinming Liu, Adam F. Abdin, Jakob Puchinger
2024 J jnl
Central Eur. J. Oper. Res.
Belma Turan, Vera C. Hemmelmayr, Allan Larsen, Jakob Puchinger
2023 J jnl
Comput. Environ. Urban Syst.
Abdelhadi Belfadel, Sebastian Hörl, Rodrigo Javier Tapia, Dimitra Politaki, Ibad Kureshi, Lóránt A. Tavasszy, Jakob Puchinger
2023 J jnl
Eur. J. Oper. Res.
Yue Su, Nicolas Dupin, Jakob Puchinger
2023 conf
MT-ITS
Tarek Chouaki, Sebastian Hörl, Jakob Puchinger
2022 J jnl
Eur. J. Oper. Res.
Ulrike Ritzinger, Jakob Puchinger, Christian Rudloff, Richard F. Hartl
2022 conf
ANT/EDI40
Ayman Mahmoud, Tarek Chouaki, Sebastian Hörl, Jakob Puchinger
2022 conf
ANT/EDI40
Tarek Chouaki, Sebastian Hörl, Jakob Puchinger
2022 J jnl
OR Spectr.
Miriam Enzi, Sophie N. Parragh, Jakob Puchinger
2022 J jnl
Eur. J. Oper. Res.
Shaohua Yu, Jakob Puchinger, Shudong Sun
2021 J jnl
Int. J. Prod. Res.
Abood Mourad, Jakob Puchinger, Tom Van Woensel
2020 J jnl
CoRR
Miriam Enzi, Sophie N. Parragh, Jakob Puchinger
2019 J jnl
CoRR
Reza Vosooghi, Joseph Kamel, Jakob Puchinger, Vincent Leblond, Marija Jankovic
2019 J jnl
Eur. J. Oper. Res.
Gerhard Hiermann, Richard F. Hartl, Jakob Puchinger, Thibaut Vidal
2019 J jnl
CoRR
Reza Vosooghi, Jakob Puchinger, Joschka Bischoff, Marija Jankovic, Anthony Vouillon
2019 J jnl
CoRR
Reza Vosooghi, Jakob Puchinger, Marija Jankovic, Anthony Vouillon
2019 J jnl
Eur. J. Oper. Res.
Tolga Bektas, Jan Fabian Ehmke, Harilaos N. Psaraftis, Jakob Puchinger
2017 conf
ITSC
Reza Vosooghi, Jakob Puchinger, Marija Jankovic, Goknur Sirin
2017 J jnl
Networks
Karl F. Doerner, Richard W. Eglese, Richard F. Hartl, Jakob Puchinger
2016 J jnl
Ann. Oper. Res.
Ulrike Ritzinger, Jakob Puchinger, Richard F. Hartl
2016 J jnl
Eur. J. Oper. Res.
Gerhard Hiermann, Jakob Puchinger, Stefan Ropke, Richard F. Hartl
2015 J jnl
Central Eur. J. Oper. Res.
Gerhard Hiermann, Matthias Prandtstetter, Andrea Rendl, Jakob Puchinger, Günther R. Raidl
2013 ch.
Hybrid Metaheuristics
Ulrike Ritzinger, Jakob Puchinger
2013 C conf
IECON
Matthias Prandtstetter, Markus Straub, Jakob Puchinger
2012 B conf
CPAIOR
Andrea Rendl, Matthias Prandtstetter, Gerhard Hiermann, Jakob Puchinger, Günther R. Raidl
2011 J jnl
Constraints An Int. J.
Jakob Puchinger, Peter J. Stuckey, Mark G. Wallace, Sebastian Brand
2011 J jnl
Appl. Soft Comput.
Christian Blum, Jakob Puchinger, Günther R. Raidl, Andrea Roli
2011 conf
OR
Christina N. Burt, Jakob Puchinger
2010 ch.
Matheuristics
Jakob Puchinger, Günther R. Raidl, Sandro Pirkwieser
2010 J jnl
INFORMS J. Comput.
Jakob Puchinger, Günther R. Raidl, Ulrich Pferschy
2009 conf
Models and Algorithms for Optimization in Logistics
Jakob Puchinger, Peter J. Stuckey, Mark Wallace, Sebastian Brand
2008 ch.
Recent Advances in Evolutionary Computation for Combinatorial Optimization
Sandro Pirkwieser, Günther R. Raidl, Jakob Puchinger
2008 C conf
PEPM
Jakob Puchinger, Peter J. Stuckey
2008 J jnl
J. Heuristics
Jakob Puchinger, Günther R. Raidl
2008 ch.
Hybrid Metaheuristics
Günther R. Raidl, Jakob Puchinger
2008 C conf
PADL
Sebastian Brand, Gregory J. Duck, Jakob Puchinger, Peter J. Stuckey
2008 B conf
CPAIOR
Jakob Puchinger, Peter J. Stuckey, Mark Wallace, Sebastian Brand
2008 conf
CATS
Samuel J. Huston, Jakob Puchinger, Peter J. Stuckey
2007 B conf
EvoCOP
Sandro Pirkwieser, Günther R. Raidl, Jakob Puchinger
2007 J jnl
Eur. J. Oper. Res.
Jakob Puchinger, Günther R. Raidl
2006 B conf
EvoCOP
Jakob Puchinger, Günther R. Raidl, Ulrich Pferschy
2005 conf
IWINAC (2)
Jakob Puchinger, Günther R. Raidl
2004 A conf
PPSN
Jakob Puchinger, Günther R. Raidl
2004 B conf
EvoCOP
Jakob Puchinger, Günther R. Raidl, Gabriele Koller
redb/extractors/decompiler/bninja/arch/x86.py
← Index redb/extractors/decompiler/bninja/arch/x86.py python
from binaryninja.enums import (
    InstructionTextTokenType,
)

# Support both package and standalone imports
try:
    from .architecture import Architecture
except ImportError:
    # Fallback to absolute imports (for multiprocessing spawned processes)
    from redb.extractors.decompiler.bninja.arch.architecture import Architecture


class Arch_x86(Architecture):
    """The concrete class for architecture-dependent details for x86_64"""

    def __init__(self):
        # general purpose registers for 64bits
        self.gpr_64 = [
            "RAX",
            "RBX",
            "RCX",
            "RDX",
            "RSI",
            "RDIR9",
            "R10",
            "R11",
            "R12",
            "R13",
            "R14",
            "R15",
        ]

        self.gpr_32 = [
            "EAX",
            "EBX",
            "ECX",
            "EDX",
            "ESI",
            "EDI",
            "R8D",
            "R9D",
            "R10D",
            "R11D",
            "R12D",
            "R13D",
            "R14D",
            "R15D",
        ]

        self.gpr_16 = [
            "AX",
            "BX",
            "CX",
            "DX",
            "SI",
            "DI",
            "R8W",
            "R9W",
            "R10W",
            "R11W",
            "R12W",
            "R13W",
            "R14W",
            "R15W",
        ]

        self.gpr_8 = [
            "AL",
            "BL",
            "CL",
            "DL",
            "SIL",
            "DIL",
            "R8B",
            "R9B",
            "R10B",
            "R11B",
            "R12B",
            "R13B",
            "R14B",
            "R15B",
        ]

        self.fpu_x87 = ["ST0", "ST1", "ST2", "ST3", "ST4", "ST5", "ST6", "ST7"]

        self.sse_xmm = [
            "XMM0",
            "XMM1",
            "XMM2",
            "XMM3",
            "XMM4",
            "XMM5",
            "XMM6",
            "XMM7",
            "XMM8",
            "XMM9",
            "XMM10",
            "XMM11",
            "XMM12",
            "XMM13",
            "XMM14",
            "XMM15",
        ]

        self.avx_ymm = [
            "YMM0",
            "YMM1",
            "YMM2",
            "YMM3",
            "YMM4",
            "YMM5",
            "YMM6",
            "YMM7",
            "YMM8",
            "YMM9",
            "YMM10",
            "YMM11",
            "YMM12",
            "YMM13",
            "YMM14",
            "YMM15",
        ]
        self.flags = ["FLAGS", "EFLAGS", "RFLAGS"]
        self.stack_registers = ["RBP", "RSP", "SP", "BP"]
        self.size = 8
        self.global_registers = (
            self.gpr_64
            + self.gpr_32
            + self.gpr_16
            + self.gpr_8
            + self.fpu_x87
            + self.sse_xmm
            + self.avx_ymm
        )
        self.opcode_categories = self._initialize_opcode_categories()

        ## instructions
        self.instructions = []

    def is_register(self, register):
        register = register.upper()
        return register in self.global_registers

    def is_general_purpose_register(self, register):
        register = register.upper()
        return (
            register in self.gpr_64
            or register in self.gpr_32
            or register in self.gpr_16
            or register in self.gpr_8
        )

    def is_stack_register(self, register):
        register = register.upper()
        return register in self.stack_registers

    def is_xmm_register(self, register):
        register = register.upper()
        return register in self.sse_xmm

    def is_control_flow(self, instr_tokens):
        return False

    def is_control_flow_instruction(self, instr_tokens):
        """Check if an instruction is a control flow instruction (jump, call, return, loop)."""
        try:
            # Extract the mnemonic from the instruction tokens
            mnemonic = None
            for token in instr_tokens:
                if token.type == InstructionTextTokenType.InstructionToken:
                    mnemonic = token.text.upper()
                    break

            if not mnemonic:
                return False

            # Check if it's a jump, call, return, or loop instruction
            return (
                mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
                or mnemonic == "CALL"  # Function calls
                or mnemonic == "RET"  # Return
                or mnemonic == "RETN"  # Another form of return
                or mnemonic.startswith("LOOP")
            )  # Loop instructions

        except Exception as e:
            print(e)
            # If we can't determine, assume it's not a control flow instruction
            return False

    def is_control_flow_instruction_by_mnemonic(self, mnemonic):
        """Check if an instruction is a control flow instruction based on its mnemonic."""
        if not mnemonic:
            return False

        mnemonic = mnemonic.upper()
        return (
            mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
            or mnemonic == "CALL"  # Function calls
            or mnemonic == "RET"  # Return
            or mnemonic == "RETN"  # Another form of return
            or mnemonic.startswith("LOOP")
        )

    def _initialize_opcode_categories(self):
        """Initialize mapping of opcodes to categories similar to Ghidra's implementation."""
        opcode_categories = {}
        opcode_index = {}  # Add this to mimic Ghidra's opcodeIndex

        # Define common opcodes array similar to Ghidra's COMMON_OPCODES
        COMMON_OPCODES = [
            # Core instructions (tracked individually)
            "MOV",
            "PUSH",
            "POP",
            "LEA",
            "CALL",
            "RET",  # Data movement and control
            "ADD",
            "SUB",
            "MUL",
            "DIV",  # Basic arithmetic
            "AND",
            "OR",
            "XOR",
            "NOT",  # Logical operations
            "JMP",
            "JE",
            "JNE",  # Basic jumps
            "TEST",
            "CMP",  # Comparisons
            # Grouped categories (aggregated tracking)
            "SIMD_MOVE",  # MOVAPS, MOVDQA, MOVDQU, etc.
            "COND_JUMP_EXT",  # Other conditional jumps (JG, JL, JGE, etc.)
            "STRING_OP",  # MOVS, STOS, LODS, SCAS, CMPS
            "STACK_ADV",  # ENTER, LEAVE, PUSHA, POPA
            "ARITHMETIC_ADV",  # IMUL, IDIV, ADC, SBB
            "BIT_OP",  # SHL, SHR, SAR, ROL, ROR, etc.
            "FPU_OP",  # FLD, FST, FADD, etc.
            "SYSTEM_OP",  # SYSCALL, INT, SYSENTER
            "CRYPTO_OP",  # AES*, SHA* instructions
            "MISC_OP",  # Rare but interesting (CPUID, RDTSC, etc.)
        ]

        # Create index map like Ghidra
        for i, opcode in enumerate(COMMON_OPCODES):
            opcode_index[opcode] = i

        # Now categorize opcodes using if/elif/else structure like in Ghidra
        for opcode in COMMON_OPCODES:
            # String Operations (checking these first to avoid MOV confusion)
            if opcode.startswith("MOVS") or opcode in [
                "STOS",
                "LODS",
                "SCAS",
                "CMPS",
                "REP",
                "REPE",
                "REPNE",
            ]:
                opcode_categories[opcode] = "STRING_MANIPULATION"

            # Data Movement (after string ops to avoid MOVS confusion)
            elif opcode.startswith("MOV") or opcode in ["LEA", "XCHG"]:
                opcode_categories[opcode] = "DATA_MOVEMENT"

            # Stack Operations
            elif opcode in ["PUSH", "POP", "ENTER", "LEAVE", "PUSHA", "POPA"]:
                opcode_categories[opcode] = "STACK_MANAGEMENT"

            # Control Flow (non-conditional)
            elif opcode in ["JMP", "CALL", "RET"]:
                opcode_categories[opcode] = "CONTROL_FLOW"

            # Conditional Jumps and Loops
            elif opcode.startswith("J") or opcode.startswith("LOOP"):
                opcode_categories[opcode] = "CONDITIONAL_JUMP"

            # Arithmetic
            elif opcode in [
                "ADD",
                "SUB",
                "MUL",
                "DIV",
                "IMUL",
                "IDIV",
                "ADC",
                "SBB",
                "INC",
                "DEC",
                "NEG",
            ]:
                opcode_categories[opcode] = "ARITHMETIC"

            # Logical
            elif opcode in ["AND", "OR", "XOR", "NOT", "TEST", "CMP"]:
                opcode_categories[opcode] = "LOGICAL"

            # Shifts & Rotates
            elif opcode in ["SHL", "SHR", "SAR", "SAL", "ROL", "ROR", "RCL", "RCR"]:
                opcode_categories[opcode] = "SHIFT_ROTATE"

            # System & Interrupts
            elif opcode in [
                "SYSCALL",
                "INT",
                "SYSENTER",
                "SYSEXIT",
                "SGDT",
                "SIDT",
                "SLDT",
                "WRMSR",
                "RDMSR",
            ]:
                opcode_categories[opcode] = "SYSTEM_CALLS"

            # Floating Point
            elif opcode.startswith("F"):
                opcode_categories[opcode] = "FPU_ARITHMETIC"

            # System Information and Random Number Generation
            elif opcode in ["PUSHF", "POPF", "CPUID", "RDTSC", "RDRAND", "RDSEED"]:
                opcode_categories[opcode] = "CPU_FEATURES"

            # Cryptography
            elif opcode.startswith("AES") or opcode.startswith("SHA"):
                opcode_categories[opcode] = "CRYPTOGRAPHIC"

            # Miscellaneous (including flag operations)
            else:
                opcode_categories[opcode] = "MISC"

        # Additional categorization for opcodes not in COMMON_OPCODES
        # This can be used in the normalize_opcode method

        # Store both maps as instance variables
        # self.opcode_categories = opcode_categories
        self.opcode_index = opcode_index

        return opcode_categories

    def is_simd_register(self, register):
        return register in self.sse_xmm