Jakob Lechner - RankMe

18 papers C 5Misc 1Journal 2Unranked 10

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Formal Verification of Spacecraft Control Programs. ACM Trans. Embed. Comput. Syst. Georgy Lukyanov, Andrey Mokhov, Jakob Lechner
2019	—	`conf`	Formal verification of spacecraft control programs (experience report). Haskell@ICFP Andrey Mokhov, Georgy Lukyanov, Jakob Lechner
2018	J	`jnl`	Formal Verification of Spacecraft Control Programs Using a Metalanguage for State Transformers. CoRR Andrey Mokhov, Georgy Lukyanov, Jakob Lechner
2018	—	`conf`	State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. DFT Markus Schütz, Andreas Steininger, Florian Huemer, Jakob Lechner
2016	C	`conf`	A new coding scheme for fault tolerant 4-phase delay-insensitive codes. ICCD Florian Huemer, Jakob Lechner, Andreas Steininger
2015	C	`conf`	Methods for analysing and improving the fault resilience of delay-insensitive codes. ICCD Jakob Lechner, Andreas Steininger, Florian Huemer
2014	—	`conf`	Protection of Muller-Pipelines from transient faults. ISQED Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger
2013	—	`conf`	An SET Tolerant Tree Arbiter Cell. ASYNC Syed Rameez Naqvi, Andreas Steininger, Jakob Lechner
2013	—	`conf`	Modular Redundancy in a GALS System Using Asynchronous Recovery Links. ASYNC Jakob Lechner, Varadan Savulimedu Veeravalli
2012	—	`conf`	A Generic Architecture for Robust Asynchronous Communication Links. PATMOS Jakob Lechner, Robert Najvirt
2012	—	`conf`	A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding. ACSD Jakob Lechner, Martin Lampacher, Thomas Polzer
2012	Misc	`conf`	Designing Robust GALS Circuits with Triple Modular Redundancy. EDCC Jakob Lechner
2012	—	`conf`	Muller C-Element Metastability Containment. PATMOS Thomas Polzer, Andreas Steininger, Jakob Lechner
2012	C	`conf`	Protecting pipelined asynchronous communication channels against single event upsets. ICCD Jakob Lechner, Martin Lampacher
2010	C	`conf`	Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. DDECS Marcus Jeitler, Jakob Lechner, Andreas Steininger
2010	C	`conf`	Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. DSD Marcus Jeitler, Jakob Lechner
2009	—	`conf`	Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation. ReConFig Marcus Jeitler, Jakob Lechner
2009	—	`conf`	Towards Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection. MEMICS Marcus Jeitler, Jakob Lechner