Jai-Ming Lin

63 papers A* 5A 18C 2Journal 23Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
Innovative Approaches to Addressing Challenges in 3D Macro Placement.
ACM Trans. Design Autom. Electr. Syst.
Jai-Ming Lin, Jia-Ting Tsai, Hsin-Lin Chen
2025 — conf
An Effective Voltage-drop Aware Analytical Placement Approach.
ACM Great Lakes Symposium on VLSI
Jai-Ming Lin, Pin-Yu Chen, Min-Chia Tsai, Chen-Fa Tsai, De-Shiun Fu, Che-Li Lin
2025 A conf
Effective Macro Placement for Very Large Scale Designs Using MCTS Guided by Pre-Trained RL.
DATE
Jai-Ming Lin, Zong-Ze Lee, Nan-Chu Lin
2025 A conf
Efficient Analytical Placement Algorithm with Hybrid Fence Region Constraints Using Non-Newtonian Fluid Model.
ICCAD
Jai-Ming Lin, Hung-Wei Hsu, Tan Huang, Chen-Fa Tsai, De-Shiun Fu, Shih-Cheng Huang
2025 — conf
IR-drop Aware Power Network Synthesis for Power Gating Designs.
ACM Great Lakes Symposium on VLSI
Jai-Ming Lin, Hsin-Lin Chen
2024 A conf
An Effective Analytical Placement Approach to Handle Fence Region Constraint.
ICCAD
Jai-Ming Lin, Wei-Yuan Lin, Yung-Chen Chen, Pin-Yu Chen, Chen-Fa Tsai, De-Shiun Fu, Che-Li Lin
2024 — conf
Timing-Driven Analytical Placement According to Expected Cell Distribution Range.
ISPD
Jai-Ming Lin, You-Yu Chang, Wei-Lun Huang
2023 A conf
HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique.
ICCAD
Jai-Ming Lin, Yu-Chien Lin, Hsuan Kung, Wei-Yuan Lin
2023 J jnl
Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Tsung-Lin Tsai, Tsung-Chun Tsai
2023 A conf
Routability-Driven Orientation-Aware Analytical Placement for System in Package.
ICCAD
Jai-Ming Lin, Tsung-Chun Tsai, Rui-Ting Shen
2023 — conf
Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network.
ISPD
Jai-Ming Lin, Yu-Tien Chen, Yang-Tai Kung, Hao-Jia Lin
2022 A conf
A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS.
ICCAD
Jai-Ming Lin, Po-Chen Lu, Heng-Yu Lin, Jia-Ting Tsai
2022 J jnl
PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Liang-Chi Zane, Min-Chia Tsai, Yung-Chen Chen, Che-Li Lin, Chen-Fa Tsai
2022 A conf
Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs.
ICCAD
Jai-Ming Lin, Hao-Yuan Hsieh, Hsuan Kung, Hao-Jia Lin
2021 — conf
A Fast Power Network Optimization Algorithm for Improving Dynamic IR-drop.
ISPD
Jai-Ming Lin, Yang-Tai Kung, Zheng-Yu Huang, I-Ru Chen
2021 A conf
DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs.
ICCAD
Jai-Ming Lin, Wei-Fan Huang, Yao-Chieh Chen, Yi-Ting Wang, Po-Wen Wang
2021 J jnl
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, You-Lun Deng, Ya-Chu Yang, Jia-Jian Chen, Po-Chen Lu
2021 A conf
Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs.
ICCAD
Jai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Che-Li Lin, Chen-Fa Tsai
2021 J jnl
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu
2021 J jnl
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu
2019 A conf
A Novel Macro Placement Approach based on Simulated Evolution Algorithm.
ICCAD
Jai-Ming Lin, You-Lun Deng, Ya-Chu Yang, Jia-Jian Chen, Yao-Chieh Chen
2019 J jnl
Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng
2019 A* conf
Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros.
DAC
Jai-Ming Lin, Szu-Ting Li, Yi-Ting Wang
2018 A conf
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models.
ICCAD
Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu
2018 A conf
Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs.
DATE
Jai-Ming Lin, Chien-yu Huang, Jhih-Ying Yang
2018 A conf
General floorplanning methodology for 3D ICs with an arbitrary bonding style.
DATE
Jai-Ming Lin, Chien-yu Huang
2018 A conf
Macro-aware row-style power delivery network design for better routability.
ICCAD
Jai-Ming Lin, Jhih-Sheng Syu, I-Ru Chen
2017 — conf
Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits.
ASP-DAC
Jai-Ming Lin, Bo-Heng Yu, Li-Yen Chang
2017 J jnl
Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jai-Ming Lin, Jung-An Yang
2016 J jnl
A Systematic Design Methodology of Asynchronous SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst.
Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang
2016 — conf
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling.
ASP-DAC
Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin
2016 J jnl
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang
2016 A conf
SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs.
ICCAD
Jai-Ming Lin, Po-Yang Chiu, Yen-Fu Chang
2015 J jnl
Placement Density Aware Power Switch Planning Methodology for Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jai-Ming Lin, Che-Chun Lin
2015 — conf
Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint.
VLSI-DAT
Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan
2014 — conf
Current density aware power switch placement algorithm for power gating designs.
ISPD
Jai-Ming Lin, Che-Chun Lin, Zong-Wei Syu, Chih-Chung Tsai, Kevin Huang
2014 J jnl
F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jai-Ming Lin, Ji-Heng Wu
2013 J jnl
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst.
Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang
2012 A conf
Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits.
ICCAD
Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, Soon-Jyh Chang
2012 J jnl
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang
2012 — conf
Routability-driven placement algorithm for analog integrated circuits.
ISPD
Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang
2012 J jnl
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Zhi-Xiong Hung
2012 — conf
Voltage island-driven floorplanning considering level shifter placement.
ASP-DAC
Jai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu
2011 A* conf
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.
DAC
Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang
2011 — conf
Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction.
ASP-DAC
Jia-Ru Chuang, Jai-Ming Lin
2011 J jnl
UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jai-Ming Lin, Zhi-Xiong Hung
2010 A* conf
Performance-driven analog placement considering boundary constraint.
DAC
Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang
2010 — conf
UFO: unified convex optimization algorithms for fixed-outline floorplanning.
ASP-DAC
Jai-Ming Lin, Hsi Hung
2005 — conf
Placement with symmetry constraints for analog layout design using TCG-S.
ASP-DAC
Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang
2005 J jnl
TCG: A transitive closure graph-based representation for general floorplans.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Yao-Wen Chang
2004 J jnl
TCG-S: orthogonal coupling of P
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jai-Ming Lin, Yao-Wen Chang
2003 J jnl
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin
2003 — conf
Graph matching-based algorithms for array-based FPGA segmentation design and routing.
ASP-DAC
Jai-Ming Lin, Song-Ra Pan, Yao-Wen Chang
2002 J jnl
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.
IEEE Trans. Very Large Scale Integr. Syst.
Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
2002 A conf
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.
DATE
Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
2002 J jnl
Performance-driven placement for dynamically reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst.
Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
2002 A* conf
TCG-S: orthogonal coupling of P
DAC
Jai-Ming Lin, Yao-Wen Chang
2001 C conf
An Algorithm for Dynamically Reconfigurable FPGA Placement.
ICCD
Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
2001 C conf
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.
ICCD
Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang
2001 J jnl
Generic ILP-based approaches for time-multiplexed FPGA partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
2001 J jnl
Matching-based algorithm for FPGA channel segmentation design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong
2001 A* conf
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.
DAC
Jai-Ming Lin, Yao-Wen Chang
1998 A conf
Graph matching-based algorithms for FPGA segmentation design.
ICCAD
Yao-Wen Chang, Jai-Ming Lin, D. F. Wong