Jafar Savoj

23 papers A* 1A 1Journal 8Unranked 13
YearRankTypeTitle / Venue / Authors
2015 — conf
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.
ISSCC
Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang
2015 J jnl
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS.
IEEE J. Solid State Circuits
Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang
2014 — conf
2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS.
ISSCC
Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, Ken Chang
2014 — conf
Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.
CICC
Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang
2013 J jnl
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs.
IEEE J. Solid State Circuits
Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang
2013 — conf
F6: Mixed-signal/RF design and modeling in next-generation CMOS.
ISSCC
Boris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu
2013 — conf
Session 10 overview: Analog techniques.
ISSCC
Jafar Savoj, Chris Mangelsdorf
2012 — conf
A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS.
VLSIC
Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang
2012 — conf
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS.
CICC
Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Zhaoyin Daniel Wu, Elad Alon, Ken Chang
2012 — conf
Session 21 overview: Analog techniques: Analog subcommittee.
ISSCC
Jafar Savoj, Chris Mangelsdorf
2012 — conf
Technologies that could change the world - You decide!
ISSCC
Jed Hurwitz, Jafar Savoj
2011 — conf
High-speed transceivers: Standards, challenges, and future.
ISSCC
Ali Sheikholeslami, Franz Dielacher, Miki Moyal, Jafar Savoj, John T. Stonick, Takuji Yamamoto
2011 J jnl
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits
Jafar Savoj, Yiannos Manoli, Hooman Darabi, Yorgos Palaskas, Michael Moyal
2008 J jnl
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications.
IEEE J. Solid State Circuits
Jafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp
2008 J jnl
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter.
IEEE J. Solid State Circuits
Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz
2007 A conf
A new technique for characterization of digital-to-analog converters in high-speed systems.
DATE
Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz
2007 — conf
Time-Variant Characterization and Compensation of Wideband Circuits.
CICC
Amir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz
2005 — conf
Clocking circuits for wireline communications.
CICC
Jafar Savoj, Ramesh Harjani
2005 J jnl
Introduction to the Special Issue on the IEEE 2004 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits
Albert Z. H. Wang, Sreedhar Natarajan, Jafar Savoj
2005 — conf
Will continued process-node shrinks kill high-performance analog design?
CICC
Jafar Savoj, David Rich, Brett Forejt, Peter R. Kinget, Un-Ku Moon, Modest M. Oprysko, Behzad Razavi, Hisashi (Sam) Shichijo, Albert Z. Wang
2003 J jnl
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector.
IEEE J. Solid State Circuits
Jafar Savoj, Behzad Razavi
2001 J jnl
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector.
IEEE J. Solid State Circuits
Jafar Savoj, Behzad Razavi
2001 A* conf
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems.
DAC
Jafar Savoj, Behzad Razavi