Jaeyong Chung - RankMe

60 papers A* 5A 3B 2C 2Misc 2Journal 37Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Variation Resilient Schemes and Approximation-Free Offset Compensation for Reliable ReRAM-Based DNN Accelerators. IEEE Trans. Emerg. Top. Comput. Je-Woo Jang, Junyong Oh, Sung-Hyuk Cho, Jae-Youn Hong, Muhammad Imran, Jaeyong Chung, Joon-Sung Yang
2025	J	`jnl`	AGD: Analytic Gradient Descent for Discrete Optimization in EDA and its Use to Gate Sizing. ACM Trans. Design Autom. Electr. Syst. Phuoc Pham, Tae-Min Park, Sung-Hyuk Cho, Tayyeb Mahmood, Joon-Sung Yang, Jaeyong Chung
2025	A*	`conf`	DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks. DAC Insu Choi, Jaeyong Chung, Joon-Sung Yang
2025	J	`jnl`	Reducing Errors and Powers in LPDDR for DNN Inference: A Compression and IECC-Based Approach. J. Syst. Archit. Jae-Youn Hong, Je-Woo Jang, Sung-Hyuk Cho, Youngbae Kong, Sungkyu Kim, Youngjung Kang, Jaehyung Ko, Jaeyong Chung, Joon-Sung Yang
2024	J	`jnl`	FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach. J. Syst. Archit. Kashif Inayat, Fahad Bin Muslim, Tayyeb Mahmood, Jaeyong Chung
2024	J	`jnl`	Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration. IEEE Trans. Very Large Scale Integr. Syst. Kashif Inayat, Inayat Ullah, Jaeyong Chung
2023	A*	`conf`	AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing. DAC Phuoc Pham, Jaeyong Chung
2023	B	`conf`	Quickloop: An Efficient, FPGA-Accelerated Exploration of Parameterized DNN Accelerators. PACT Tayyeb Mahmood, Kashif Inayat, Jaeyong Chung
2022	J	`jnl`	Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration. IEEE Trans. Very Large Scale Integr. Syst. Kashif Inayat, Jaeyong Chung
2021	J	`jnl`	Training Multi-Bit Quantized and Binarized Networks with a Learnable Symmetric Quantizer. IEEE Access Phuoc Pham, Jacob A. Abraham, Jaeyong Chung
2021	J	`jnl`	Training Multi-bit Quantized and Binarized Networks with A Learnable Symmetric Quantizer. CoRR Phuoc Pham, Jacob A. Abraham, Jaeyong Chung
2020	J	`jnl`	ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Inayat Ullah, Joon-Sung Yang, Jaeyong Chung
2020	A*	`conf`	Factored Radix-8 Systolic Array for Tensor Processing. DAC Inayat Ullah, Kashif Inayat, Joon-Sung Yang, Jaeyong Chung
2020	A	`conf`	Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture. DATE Jeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung-Hee Cho, Jaeyong Chung, Joon-Sung Yang
2020	J	`jnl`	Virtualization-Based Efficient TSV Repair for 3-D Integrated Circuits. IEEE Access Muhammad Imran, Hyunseung Han, Jooho Kim, Taehyun Kwon, Jaeyong Chung, Joon-Sung Yang
2019	J	`jnl`	DeepRT: predictable deep learning inference for cyber-physical systems. Real Time Syst. Woochul Kang, Jaeyong Chung
2019	J	`jnl`	Physical Workout Classification Using Wrist Accelerometer Data by Deep Convolutional Neural Networks. IEEE Access Pilyeong Jeong, Mungyeong Choe, Nahyeong Kim, Jaehyun Park, Jaeyong Chung
2019	J	`jnl`	Power- and Time-Aware Deep Learning Inference for Mobile Embedded Devices. IEEE Access Woochul Kang, Jaeyong Chung
2019	J	`jnl`	Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaeyong Chung, Taehwan Shin, Joon-Sung Yang
2019	J	`jnl`	Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yongshin Kang, Joon-Sung Yang, Jaeyong Chung
2018	J	`jnl`	Dynamic Fixed-Point Design of Neuromorphic Computing Systems. IEICE Trans. Electron. Yongshin Kang, Jaeyong Chung
2018	J	`jnl`	Mitigating Observability Loss of Toggle-Based X-Masking via Scan Chain Partitioning. IEEE Trans. Computers Sae-Eun Kim, Jaeyong Chung, Joon-Sung Yang
2018	J	`jnl`	New library development method by FSM based cell pattern extraction. IEICE Electron. Express Byung-Su Kim, Tae Hee Han, Joon-Sung Yang, Jaeyong Chung
2018	J	`jnl`	READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution. IEEE Trans. Computers Hyunseung Han, Jaeyong Chung, Joon-Sung Yang
2017	—	`conf`	A dynamic fixed-point representation for neuromorphic computing systems. ISOCC Yongshin Kang, Jaeyong Chung
2017	J	`jnl`	Energy-efficient response time management for embedded databases. Real Time Syst. Woochul Kang, Jaeyong Chung
2017	J	`jnl`	Exploiting Sparse Activation for Low-Power Design of Synchronous Neuromorphic Systems. IEICE Trans. Electron. Jaeyong Chung, Woochul Kang
2017	A	`conf`	Synthesis of activation-parallel convolution structures for neuromorphic architectures. DATE Seban Kim, Jaeyong Chung
2016	J	`jnl`	Defect Diagnosis via Segment Delay Learning. IEEE Trans. Very Large Scale Integr. Syst. Jaeyong Chung, Woochul Kang
2016	C	`conf`	Live demonstration: Real-time image classification on a neuromorphic computing system with zero off-chip memory access. ISCAS Taehwan Shin, Yongshin Kang, Seungho Yang, Seban Kim, Jaeyong Chung
2016	A*	`conf`	Simplifying deep neural networks for neuromorphic architectures. DAC Jaeyong Chung, Taehwan Shin
2015	J	`jnl`	Bit-Width Optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems. IEEE Trans. Computers Jaeyong Chung, Lok-Won Kim
2015	J	`jnl`	Delay Defect Diagnosis Methodology Using Path Delay Measurements. IEICE Trans. Electron. Eun Jung Jang, Jaeyong Chung, Jacob A. Abraham
2015	J	`jnl`	INsight: A Neuromorphic Computing System for Evaluation of Large Neural Networks. CoRR Jaeyong Chung, Taehwan Shin, Yongshin Kang
2015	J	`jnl`	QoS Management for Embedded Databases in Multicore-Based Embedded Systems. Mob. Inf. Syst. Woochul Kang, Jaeyong Chung
2015	J	`jnl`	Segment Delay Learning From Quantized Path Delay Measurements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaeyong Chung, Jibum Kim
2015	J	`jnl`	Untangling polygonal and polyhedral meshes via mesh optimization. Eng. Comput. Jibum Kim, Jaeyong Chung
2014	J	`jnl`	3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaeyong Chung, Yonghyun Kim, Joon-Sung Yang
2013	J	`jnl`	A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories. IEEE Trans. Very Large Scale Integr. Syst. Jaeyong Chung, Joonsung Park, Jacob A. Abraham
2013	J	`jnl`	Concurrent Path Selection Algorithm in Statistical Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. Jaeyong Chung, Jacob A. Abraham
2012	J	`jnl`	On Computing Criticality in Refactored Timing Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaeyong Chung, Jacob A. Abraham
2012	J	`jnl`	Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham
2012	J	`jnl`	Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaeyong Chung, Jacob A. Abraham
2012	J	`jnl`	Temporal Presence Variation in Immersive Computer Games. Int. J. Hum. Comput. Interact. Jaeyong Chung, Henry J. Gardner
2012	J	`jnl`	Testability-Driven Statistical Path Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham
2011	J	`jnl`	Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. J. Electron. Test. Kihyuk Han, Joonsung Park, Jae Wook Lee, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, Sejang Oh, Jacob A. Abraham
2011	—	`conf`	Path criticality computation in parameterized statistical timing analysis. ASP-DAC Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham
2011	—	`conf`	Post-Silicon Timing Validation Method Using Path Delay Measurements. Asian Test Symposium Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham
2011	A*	`conf`	Testability driven statistical path selection. DAC Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham
2010	B	`conf`	A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. ETS HyunJin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo
2010	—	`conf`	At-speed Test of High-Speed DUT Using Built-Off Test Interface. Asian Test Symposium Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh
2010	Misc	`conf`	Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate. VTS Jaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo
2009	A	`conf`	A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA. ICCAD Jaeyong Chung, Jacob A. Abraham
2009	—	`conf`	LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits. Asian Test Symposium Joonsung Park, Jaeyong Chung, Jacob A. Abraham
2009	—	`conf`	Measuring temporal variation in presence during game playing. VRCAI Jaeyong Chung, Henry J. Gardner
2009	Misc	`conf`	Recursive Path Selection for Delay Fault Testing. VTS Jaeyong Chung, Jacob A. Abraham
2006	C	`conf`	A Dynamic Load Balancing for Massive Multiplayer Online Game Server. ICEC Jungyoul Lim, Jaeyong Chung, Jin Ryong Kim, Kwanghyun Shim
2006	—	`conf`	Color Object Tracking System for Interactive Entertainment Applications. ICASSP (5) Jaeyong Chung, Kwanghyun Shim
2004	—	`conf`	VENUS: The Online Game Simulator Using Massively Virtual Clients. AsiaSim YungWoo Jung, Bum-Hyun Lim, Kwanghyun Sim, Hunjoo Lee, Ilkyu Park, Jaeyong Chung, Jihong Lee
2003	—	`conf`	Driving Virtual Human using the Hybrid of Position-based and Angle-based Control Mode. Modelling, Simulation, and Optimization Jaeyong Chung, Gwanghyun Shim, Byungtae Choi