Jaemin Jang

15 papers A* 2Journal 11Unranked 2
YearRankTypeTitle / Venue / Authors
2024 — conf
13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.
ISSCC
Jinhyung Lee, Kyungjun Cho, Chang Kwon Lee, Yeonho Lee, Jae-Hyung Park, Su-Hyun Oh, Yucheon Ju, Chunseok Jeong, Ho Sung Cho, Jaeseung Lee, Tae-Sik Yun, Jin Hee Cho, Sangmuk Oh, Junil Moon, Young-Jun Park, Hong-Seok Choi, In-Keun Kim, Seung Min Yang, Sun-Yeol Kim, Jaemin Jang, Jinwook Kim, Seong-Hee Lee, Younghyun Jeon, Juhyung Park, Tae-Kyun Kim, Dongyoon Ka, Sanghoon Oh, Jinse Kim, Junyeol Jeon, Seonhong Kim, Kyeong Tae Kim, Taeho Kim, Hyeonjin Yang, Dongju Yang, Minseop Lee, Heewoong Song, Dongwook Jang, Junghyun Shin, Hyunsik Kim, Chang-Ki Baek, Hajun Jeong, Jongchan Yoon, Seung-Kyun Lim, Kyo Yun Lee, Young Jun Koo, Myeong-Jae Park, Joohwan Cho, Jonghwan Kim
2019 J jnl
DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells.
IEEE Trans. Computers
Jungwhan Choi, Jaemin Jang, Lee-Sup Kim
2019 J jnl
Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory.
IEEE Trans. Computers
Jaemin Jang, Wongyu Shin, Jungwhan Choi, Yongju Kim, Lee-Sup Kim
2018 J jnl
Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs.
IEEE Trans. Computers
Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Hakseung Lee, Lee-Sup Kim
2017 J jnl
A new application-layer overlay platform for better connected vehicles.
Int. J. Distributed Sens. Networks
Jaemin Jang, Taemin Ahn, Junghee Han
2017 J jnl
Bank-Group Level Parallelism.
IEEE Trans. Computers
Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim
2017 J jnl
In-DRAM Data Initialization.
IEEE Trans. Very Large Scale Integr. Syst.
Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim
2017 J jnl
Rank-Level Parallelism in DRAM.
IEEE Trans. Computers
Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim
2017 J jnl
Refresh-Aware Write Recovery Memory Controller.
IEEE Trans. Computers
Jaemin Jang, Wongyu Shin, Jungwhan Choi, Jinwoong Suh, Yongkee Kwon, Yongju Kim, Lee-Sup Kim
2016 J jnl
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs.
IEEE Trans. Circuits Syst. II Express Briefs
Ji-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae-Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2016 J jnl
DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing.
IEEE Trans. Computers
Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Youngsuk Moon, Yongkee Kwon, Lee-Sup Kim
2016 A* conf
Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity.
ISCA
Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim
2016 J jnl
Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation.
IEEE Trans. Computers
Wongyu Shin, Jungwhan Choi, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Hongsik Kim, Lee-Sup Kim
2015 A* conf
Multiple clone row DRAM: a low latency and area optimized DRAM.
ISCA
Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim
2012 — conf
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.
ISSCC
Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, HyeYoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yong-Ju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim