Jaejin Park - RankMe

19 papers A 1C 2Journal 6Unranked 10

Year	Rank	Type	Title / Venue / Authors
2017	J	`jnl`	A 0.015-mm IEEE Trans. Circuits Syst. II Express Briefs Gyu-Seob Jeong, Wooseok Kim, Jaejin Park, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
2016	—	`conf`	Session 12 overview: Efficient Power Conversion. ISSCC Vadim Ivanov, Jaejin Park
2014	—	`conf`	15.2 A 0.012mm ISSCC Jenlung Liu, Tae-Kwang Jang, Yonghee Lee, Jungeun Shin, Seunghoon Lee, Taeik Kim, Jaejin Park, Hojin Park
2014	J	`jnl`	Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. IEEE J. Solid State Circuits Wooseok Kim, Jaejin Park, Hojin Park, Deog-Kyoon Jeong
2013	—	`conf`	A 0.026mm ISSCC Tae-Kwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park
2013	—	`conf`	A 0.032mm ISSCC Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, Deog-Kyoon Jeong
2013	A	`conf`	Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization. ICCAD Taehwan Kim, Do-Gyoon Song, Sangho Youn, Jaejin Park, Hojin Park, Jaeha Kim
2012	—	`conf`	A 0.004mm ISSCC Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park
2012	—	`conf`	An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. ISSCC Pyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho
2011	—	`conf`	A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS. A-SSCC Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang, Dohyung Kim, Jihyun F. Kim, Jaejin Park, Hojin Park
2008	J	`jnl`	CFGP: a web-based, comparative fungal genomics platform. Nucleic Acids Res. Jongsun Park, Bongsoo Park, Kyongyong Jung, Suwang Jang, Kwangyul Yu, Jaeyoung Choi, Sunghyung Kong, Jaejin Park, Seryun Kim, Hyojeong Kim, Soonok Kim, Jihyun F. Kim, Jaime E. Blair, Kwangwon Lee, Seogchan Kang, Yong-Hwan Lee
2008	J	`jnl`	FTFD: an informatics pipeline supporting phylogenomic analysis of fungal transcription factors. Bioinform. Jongsun Park, Jaejin Park, Suwang Jang, Seryun Kim, Sunghyung Kong, Jaeyoung Choi, Kyohun Ahn, Juhyeon Kim, Seungmin Lee, Sunggon Kim, Bongsoo Park, Kyongyong Jung, Soonok Kim, Seogchan Kang, Yong-Hwan Lee
2007	—	`conf`	A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR. CICC Jaejin Park, J. F. Liu, L. Richard Carley, C. Patrick Yue
2005	—	`conf`	A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs. ISCAS (2) Jaejin Park, Ruifeng Sun, L. Rick Carley, C. Patrick Yue
2005	—	`conf`	A low-power, 20-Gb/s continuous-time adaptive passive equalizer. ISCAS (2) Ruifeng Sun, Jaejin Park, Frank O'Mahony, C. Patrick Yue
2000	C	`conf`	A 1 mW 10-bit 500KSPS SAR A/D converter. ISCAS Jaejin Park, Ho-Jin Park, Jae-Whui Kim, Sangnam Seo, Philip Chung
1999	J	`jnl`	A 5-MHz IF digital FM demodulator. IEEE J. Solid State Circuits Jaejin Park, Eurho Joe, Myung-Jun Choe, Bang-Sup Song
1995	J	`jnl`	A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem. IEEE J. Solid State Circuits Daejeong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim
1994	C	`conf`	A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter. ISCAS Daejong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim