Jaehyouk Choi - RankMe

82 papers C 1Misc 1Journal 39Unranked 40

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces. IEEE J. Solid State Circuits Jaeho Kim, Myeongho Han, Hyunjun Song, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
2025	—	`conf`	22.2: An 850µW 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces. ISSCC Jeongbeom Seo, Yoonseo Cho, Yuhwan Shin, Jaehyouk Choi
2025	—	`conf`	34.1 A 65fsrms-Jitter and -272dB-FoMjitter, N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration. ISSCC Munjae Chae, Seheon Jang, Chanwoong Hwang, Hangi Park, Jaehyouk Choi
2025	—	`conf`	8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time. ISSCC Jaeho Kim, Myeongho Han, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
2025	J	`jnl`	A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator. IEEE J. Solid State Circuits Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi
2025	J	`jnl`	A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique. IEEE Solid State Circuits Lett. Sungjin Kim, Jeonghyun Lee, Yoonseo Cho, Jintae Kim, Jaehyouk Choi, Heein Yoon
2025	J	`jnl`	A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces. IEEE J. Solid State Circuits Yuhwan Shin, Yongwoo Jo, Juyeop Kim, Junseok Lee, Jongwha Kim, Jaehyouk Choi
2025	J	`jnl`	A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration. IEEE J. Solid State Circuits Munjae Chae, Seheon Jang, Seungjae Lee, Jaehyouk Choi
2025	J	`jnl`	A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer With a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier. IEEE J. Solid State Circuits Seohee Jung, Jaeho Kim, Jooeun Bang, Sarang Lee, Heein Yoon, Jaehyouk Choi
2025	J	`jnl`	A Low-Reference-Spur and Low-Jitter D-Band PLL With Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector. IEEE Solid State Circuits Lett. Jaeho Kim, Jooeun Bang, Seohee Jung, Myeongho Han, Jaehyouk Choi
2024	—	`conf`	10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. ISSCC Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi
2024	—	`conf`	10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique. ISSCC Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi
2024	—	`conf`	A -51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector. A-SSCC Jaeho Kim, Jooeun Bang, Seohee Jung, Myeongho Han, Jaehyouk Choi
2024	J	`jnl`	A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation. IEEE J. Solid State Circuits Juyeop Kim, Yongwoo Jo, Hangi Park, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2024	J	`jnl`	A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm. IEEE J. Solid State Circuits Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi
2023	—	`conf`	A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth. ISSCC Jooeun Bang, Jaeho Kim, Seohee Jung, Suneui Park, Jaehyouk Choi
2023	—	`conf`	A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter. CICC Jeonghyun Lee, Yoonseo Cho, Jintae Kim, Jaehyouk Choi
2023	—	`conf`	A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique. VLSI Technology and Circuits Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi
2023	—	`conf`	A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier. ISSCC Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Chanwoong Hwang, Hangi Park, Jaehyouk Choi
2023	—	`conf`	A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL. ISSCC Byeong-Taek Moon, Sang-Gug Lee, Jaehyouk Choi
2023	—	`conf`	A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25 ISSCC Yuhwan Shin, Yongwoo Jo, Juyeop Kim, Junseok Lee, Jongwha Kim, Jaehyouk Choi
2023	J	`jnl`	A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68. IEEE J. Solid State Circuits Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi
2023	J	`jnl`	A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier. IEEE J. Solid State Circuits Yongwoo Jo, Juyeop Kim, Yuhwan Shin, Hangi Park, Chanwoong Hwang, Younghyun Lim, Jaehyouk Choi
2022	—	`conf`	A 188fsrms-Jitter and -243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. ISSCC Chanwoong Hwang, Hangi Park, Taeho Seong, Jaehyouk Choi
2022	—	`conf`	A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator. ISSCC Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi
2022	J	`jnl`	A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. IEEE J. Solid State Circuits Hangi Park, Chanwoong Hwang, Taeho Seong, Jaehyouk Choi
2022	J	`jnl`	A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. IEEE J. Solid State Circuits Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi
2022	J	`jnl`	A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop. IEEE J. Solid State Circuits Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Jaehyouk Choi
2022	J	`jnl`	An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. IEEE J. Solid State Circuits Suneui Park, Seojin Choi, Seyeon Yoo, Yoonseo Cho, Jaehyouk Choi
2021	—	`conf`	32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique. ISSCC Juyeop Kim, Yongwoo Jo, Younghyun Lim, Taeho Seong, Hangi Park, Seyeon Yoo, Yongsun Lee, Seojin Choi, Jaehyouk Choi
2021	—	`conf`	A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency. ESSCIRC Jooeun Bang, Seojin Choi, Seyeon Yoo, Jeonghyun Lee, Juyeop Kim, Jaehyouk Choi
2021	—	`conf`	A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping Δ ΣM. ISSCC Hangi Park, Chanwoong Hwang, Taeho Seong, Yongsun Lee, Jaehyouk Choi
2021	J	`jnl`	A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. IEEE J. Solid State Circuits Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2021	—	`conf`	An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS. ISSCC Seyeon Yoo, Suneui Park, Seojin Choi, Yoonseo Cho, Heein Yoon, Chanwoong Hwang, Jaehyouk Choi
2021	—	`conf`	Session 32 Overview: Frequency Synthesizers Rf Subcommittee. ISSCC Wei Deng, Jaehyouk Choi, Wanghua Wu
2020	—	`conf`	17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction. ISSCC Yongsun Lee, Taeho Seong, Jeonghyun Lee, Chanwoong Hwang, Hangi Park, Jaehyouk Choi
2020	—	`conf`	17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word. ISSCC Taeho Seong, Yongsun Lee, Chanwoong Hwang, Jeonghyun Lee, Hangi Park, Kyuho Jason Lee, Jaehyouk Choi
2020	—	`conf`	17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator. ISSCC Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Seyeon Yoo, Hangi Park, Heein Yoon, Jaehyouk Choi
2020	J	`jnl`	Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits David T. Blaauw, Hoi Lee, John P. Keane, Jaehyouk Choi, Sudhakar Pamarti
2019	—	`conf`	A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer. VLSI Circuits Jeonghyun Lee, Jooeun Bang, Younghyun Lim, Jaehyouk Choi
2019	—	`conf`	A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator. ISSCC Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, Jaehyouk Choi
2019	J	`jnl`	A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC. IEEE J. Solid State Circuits Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
2019	—	`conf`	A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization. ISSCC Juyeop Kim, Heein Yoon, Younghyun Lim, Yongsun Lee, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2019	J	`jnl`	A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration. IEEE J. Solid State Circuits Heein Yoon, Suneui Park, Jaehyouk Choi
2019	J	`jnl`	An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114. IEEE J. Solid State Circuits Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi
2019	J	`jnl`	An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators. IEEE J. Solid State Circuits Juyeop Kim, Younghyun Lim, Heein Yoon, Yongsun Lee, Hangi Park, Yoonseo Cho, Taeho Seong, Jaehyouk Choi
2018	—	`conf`	153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier. VLSI Circuits Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi
2018	—	`conf`	A -242dB FOM and -75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC. ISSCC Taeho Seong, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
2018	—	`conf`	A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers. ISSCC Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi
2018	—	`conf`	A 320µV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector. ESSCIRC Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seyeon Yoo, Jaehyouk Choi
2018	J	`jnl`	A 65-nm CMOS 2×2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations. IEEE J. Solid State Circuits Kyoohyun Lim, Sanghoon Lee, Yongha Lee, Byeongmoo Moon, Hwahyeong Shin, Kisub Kang, Seungbeom Kim, Jinhyeok Lee, Hyungsuk Lee, Hyunchul Shim, Chulhoon Sung, Kumyoung Park, Garam Lee, Minjung Kim, Seokyeong Park, Hyosun Jung, Younghyun Lim, Changhun Song, Jaehyeon Seong, Heechang Cho, Jaehyouk Choi, Jong-Ryul Lee, Sangwoo Han
2018	J	`jnl`	A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers. IEEE J. Solid State Circuits Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
2018	J	`jnl`	A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique. IEEE J. Solid State Circuits Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi
2018	—	`conf`	A switched-loop-filter PLL with fast phase-error correction technique. ASP-DAC Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi
2018	J	`jnl`	An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique. IEEE J. Solid State Circuits Younghyun Lim, Jeonghyun Lee, Suneui Park, Yongwoo Jo, Jaehyouk Choi
2018	—	`conf`	An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate. ASP-DAC Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi
2018	—	`conf`	Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers. ASP-DAC Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
2018	—	`conf`	Session 15 overview: RF PLLs: RF subcommittee. ISSCC Jiayoon Ru, Jaehyouk Choi, Piet Wambacq
2017	—	`conf`	19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers. ISSCC Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi
2017	J	`jnl`	An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current. IEEE Trans. Very Large Scale Integr. Syst. Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seong-Sik Song, Hong-Teuk Kim, Ockgoo Lee, Jaehyouk Choi
2017	—	`conf`	An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate. CICC Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi
2017	—	`conf`	An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration. A-SSCC Suneui Park, Heein Yoon, Jaehyouk Choi
2016	—	`conf`	10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector. ISSCC Seojin Choi, Seyeon Yoo, Jaehyouk Choi
2016	J	`jnl`	A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers. IEEE J. Solid State Circuits Heein Yoon, Yongsun Lee, Younghyun Lim, Geum-Young Tak, Hong-Teuk Kim, Yo-Chuol Ho, Jaehyouk Choi
2016	J	`jnl`	A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells. IEEE J. Solid State Circuits Mina Kim, Seojin Choi, Taeho Seong, Jaehyouk Choi
2016	J	`jnl`	A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector. IEEE J. Solid State Circuits Seojin Choi, Seyeon Yoo, Younghyun Lim, Jaehyouk Choi
2016	—	`conf`	A PVT-robust -59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop. VLSI Circuits Yongsun Lee, Heein Yoon, Mina Kim, Jaehyouk Choi
2015	—	`conf`	A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells. VLSIC Mina Kim, Seojin Choi, Jaehyouk Choi
2015	J	`jnl`	A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. Yongsun Lee, Mina Kim, Taeho Seong, Jaehyouk Choi
2015	J	`jnl`	A Reconfigurable Multiphase $LC$-Ring Structure for Programmable Frequency Multiplication. IEEE Trans. Circuits Syst. II Express Briefs Donguk Kim, Subin Choi, Jaehyouk Choi, Jae Joon Kim
2015	J	`jnl`	A Wide-Range On-Chip Leakage Sensor Using a Current-Frequency Converting Technique in 65-nm Technology Node. IEEE Trans. Circuits Syst. II Express Briefs Yesung Kang, Jaehyouk Choi, Youngmin Kim
2015	J	`jnl`	Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers. IEEE Trans. Circuits Syst. I Regul. Pap. Taeho Seong, Jae Joon Kim, Jaehyouk Choi
2015	Misc	`conf`	Optimization of analog circuits via simulation and a lagrangian-type gradient-based method. WSC Eunji Lim, Youngmin Kim, Jaehyouk Choi
2014	J	`jnl`	A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core. IEEE Trans. Circuits Syst. II Express Briefs Heein Yoon, Yongsun Lee, Jae Joon Kim, Jaehyouk Choi
2014	J	`jnl`	Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration. IEEE Trans. Circuits Syst. II Express Briefs Taeho Seong, Yongsun Lee, Jaehyouk Choi
2013	J	`jnl`	A CMOS Highly Linear Hybrid Current/Voltage Controlled Oscillator for Wideband Polar Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. Yiwu Tang, Jianyun Hu, Jongmin Park, Jaehyouk Choi, Lincoln Leung, Chiewcharn Narathong, Kamal Sahota
2012	—	`conf`	A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulation. CICC Yiwu Tang, Jianyun Hu, Jongmin Park, Jaehyouk Choi, Lincoln Leung, Chiewcharn Narathong, Kamal Sahota
2012	J	`jnl`	A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL. IEEE Trans. Very Large Scale Integr. Syst. Jaehyouk Choi, Woonyun Kim, Kyutae Lim
2011	J	`jnl`	A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor. IEEE Trans. Very Large Scale Integr. Syst. Jaehyouk Choi, Stephen T. Kim, Woonyun Kim, Kwan-Woo Kim, Kyutae Lim, Joy Laskar
2010	J	`jnl`	A 122-mW Low-Power Multiresolution Spectrum-Sensing IC With Self-Deactivated Partial Swing Techniques. IEEE Trans. Circuits Syst. II Express Briefs Taejoong Song, Jongmin Park, Sang Min Lee, Jaehyouk Choi, Kihong Kim, Chang-Ho Lee, Kyutae Lim, Joy Laskar
2010	—	`—`	Fully-integrated DLL/PLL-based CMOS frequency synthesizers for wireless systems. Jaehyouk Choi
2010	C	`conf`	Subthreshold current mode matrix determinant computation for analog signal processing. ISCAS Stephen T. Kim, Jaehyouk Choi, Sungho Beck, Taejoong Song, Kyutae Lim, Joy Laskar