Jaeduk Han - RankMe

80 papers A 1C 5Journal 40Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 36-Gb/s Single-Ended PAM-4 Receiver With Voltage-Feedback DFE in 40-nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Taeyang Sim, Geunyoung You, Hwanseok Jung, Donghun Lee, Taeho Shin, Jaeduk Han
2026	J	`jnl`	A 6-GS/s 8-bit Time-Domain ADC With Selection-First Pipelined Successive Approximation Register TDC in 28-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Dongjun Lee, Bona Lim, Yonghwa Kwon, Jaeduk Han
2025	J	`jnl`	100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology. IEEE J. Solid State Circuits Eunji Song, Jeonghyu Yang, Youngmin Oh, Seungwook Hong, Dongjun Lee, Sangwan Lee, Hyunwoo Im, Taeho Shin, Jaeduk Han
2025	—	`conf`	22.4 A 32-to-50Gb/s/pin Single-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding. ISSCC Yunseong Jo, Hyuntae Kim, Young Choi, Jaewoo Park, Myoungbo Kwak, Jaeduk Han
2025	—	`conf`	A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology. ASP-DAC Yunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han
2025	C	`conf`	A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees. ISCAS Yooseong Jang, Seokmin Yun, Jeonghyu Yang, Taeho Shin, Eunji Song, Jaeduk Han
2025	J	`jnl`	A 96-Gb/s 1.6-V IEEE Trans. Very Large Scale Integr. Syst. Taeseung Kang, Jeonghyu Yang, Eunji Song, Seungwoo Son, Hyuntae Kim, Jaeduk Han
2025	C	`conf`	A 96-Gb/s PAM-8 Transmitter with Transition-Boosted Current-Mode Logic Driver in 40-nm CMOS for Wireline Communication. ISCAS Bona Lim, Hanhee Jo, Heedo Jeong, Jeonghyu Yang, Jaeduk Han
2025	J	`jnl`	A Driver-Current-Regulated 120-Gb/s PAM-8 7-bit DAC-Based Transmitter in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Taeho Shin, Yooseong Jang, Seokmin Yun, Jeonghyu Yang, Jaeduk Han
2025	J	`jnl`	A Flying-Capacitor-Assisted Single-Mode Buck-Boost Converter for Battery-Powered Applications. IEEE Trans. Very Large Scale Integr. Syst. Sunghae Kim, Taehee Lee, Kunhee Cho, Jaeduk Han
2025	J	`jnl`	A Variation-Robust 20-Gb/s Wireline Transceiver With Real-Time Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Sangwan Lee, Hyeongmin Seo, Wookjin Shin, Dongju Yang, Gaeryun Sung, Sanghun Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Ickhyun Song, Jaeduk Han
2025	—	`conf`	Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFET. SMACD Taeseung Kang, Taeho Shin, Heejun Kim, Jaeduk Han
2025	—	`conf`	WDP: A Weighted Delay Prediction Method for Integrated Circuit Interconnects. SMACD Yoonsoo Park, Songnam Hong, Jaeduk Han
2024	J	`jnl`	3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction. IEEE Trans. Circuits Syst. II Express Briefs Gijin Park, Sun-Ho Yeom, InWoo Jang, Dongjun Lee, Jaeduk Han, Min-Seong Choo
2024	J	`jnl`	A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Youngmin Oh, Hyunwoo Im, Jeonghyu Yang, Eunji Song, Dongjun Lee, Sangwan Lee, Taeho Shin, Jaeduk Han
2024	J	`jnl`	A 102-Gb/s/lane 1.4-V IEEE Trans. Circuits Syst. II Express Briefs Sangwan Lee, Hyeongmin Seo, Seungwoo Son, Sunoh Yeom, Jaeduk Han
2024	C	`conf`	A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. ISCAS Zhongkai Wang, Minsoo Choi, Paul Kwon, Zhaokai Liu, Bozhi Yin, Kyoungtae Lee, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon
2024	J	`jnl`	A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Taeyang Sim, Sun-Ho Yeom, Hyunwoo Im, Youngmin Oh, Hyeongmin Seo, Hyeongjun Ko, Hankyu Chi, Hae-Kang Jung, Jaeduk Han
2024	J	`jnl`	A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. Hyuntae Kim, Yunseong Jo, Sanghun Lee, Eunsang Lee, Young Choi, Jaewoo Park, Myoungbo Kwak, Jung-Hwan Choi, Youngdon Choi, Jaeduk Han
2024	J	`jnl`	A 35-Gb/s PAM-4 Transmitter With 7B4Q Full-Transition Avoidance and Area-Efficient Gm-Boosting Techniques. IEEE Trans. Circuits Syst. II Express Briefs Eunji Song, Jiyun Han, Hyeongmin Seo, Hyuntae Kim, Hyunwoo Im, Jaeduk Han
2024	J	`jnl`	A PSRR-Enhanced Fast-Response Inverter-Based LDO for Mobile Devices. IEEE Trans. Circuits Syst. II Express Briefs Sanghun Lee, Jaemyung Lim, Jaeduk Han
2024	J	`jnl`	A Variation-Tolerant Voltage-Mode Transmitter With 3+1 Tap FFE in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Wookjin Shin, Hyeongmin Seo, Sangwan Lee, Dong-Ho Choi, Young-Ho Kwak, Soon-Jae Won, Jaeduk Han
2024	J	`jnl`	Analog Circuit Design Automation via Sequential RL Agents and Gm/ID Methodology. IEEE Access Sungweon Hong, Yunseob Tae, Dongjun Lee, Gijin Park, Jaemyung Lim, Kyungjun Cho, Chunseok Jeong, Myeong-Jae Park, Songnam Hong, Jaeduk Han
2024	—	`conf`	Analysis of Test Environment Configuration for High-Speed Link Chip Measurement. ISOCC Yunseong Jo, Hyuntae Kim, Jaeduk Han
2024	J	`jnl`	Interactive and Automatic Generation of Primitive Custom Circuit Layout Using LLMs. CoRR Geunyoung You, Youjin Byun, Sojin Lim, Jaeduk Han
2024	—	`conf`	Low-Power Encoding for PAM-3 DRAM Bus. SMACD Jonghyeon Nam, Jaeduk Han, Hokeun Kim
2024	J	`jnl`	Low-Power Encoding for PAM-3 DRAM Bus. CoRR Jonghyeon Nam, Jaeduk Han, Hokeun Kim
2024	—	`conf`	Non-parametric Sensor Noise Modeling and Synthesis. ECCV (24) Ali Mosleh, Luxi Zhao, Atin Singh, Jaeduk Han, Abhijith Punnappurath, Marcus A. Brubaker, Jihwan Choe, Michael S. Brown
2023	—	`conf`	A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm. ISSCC Jeonghyu Yang, Eunji Song, Seungwook Hong, Dongjun Lee, Sangwan Lee, Hyunwoo Im, Taeho Shin, Jaeduk Han
2023	J	`jnl`	A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. IEEE Trans. Circuits Syst. II Express Briefs Hyeongmin Seo, Jiyun Han, Kyungmin Kim, Baek-Jin Lim, EunSeok Shin, Youngdon Choi, Hyungjong Ko, Jung-Hwan Choi, Sang-Hyun Lee, Changsik Yoo, Jaeduk Han
2023	J	`jnl`	A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Hyochang Kim, Hyeongmin Seo, Hyuntae Kim, Changsik Yoo, Jaeduk Han
2023	J	`jnl`	An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Hyuntae Kim, Hyeongmin Seo, Yunseong Jo, Changsik Yoo, Jaeduk Han
2023	—	`conf`	An Analysis of CMOS Latched Comparators. ICEIC Sun-Ho Yeom, Taeyang Sim, Jaeduk Han
2023	—	`conf`	An Analysis of Current-mode Drivers in 40-nm CMOS Technology. ISOCC Bona Lim, Hanhee Jo, Jaeduk Han
2023	J	`jnl`	An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies. IEEE Access Dongjun Lee, Gijin Park, Jaeduk Han, Min-Seong Choo
2023	—	`conf`	Analysis of Grounded Coplanar Waveguide (GCPW) for High-Speed Links Channel. ISOCC Youngmin Oh, Taeyang Sim, Jaeduk Han
2023	J	`jnl`	LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taeho Shin, Dongjun Lee, Dongwhee Kim, Gaeryun Sung, Wookjin Shin, Yunseong Jo, Hyungjoo Park, Jaeduk Han
2023	—	`conf`	Multi-Phase Frequency Divider Generator with Process-Independent Automation. ISOCC Jihoon Jang, Heedo Jeong, Jaeduk Han
2023	J	`jnl`	Precursor ISI Cancellation Sliding-Block DFE for High-Speed Wireline Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. Kunmo Kim, Suhong Moon, Jaeduk Han, Elad Alon, Ali M. Niknejad
2022	J	`jnl`	A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Eunsang Lee, Changhyun Pyo, Sanghun Lee, Jaeduk Han
2022	—	`conf`	A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. VLSI Technology and Circuits Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon
2022	—	`conf`	A 32-Gb/s High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-drivers in 40-nm CMOS for Short-Reach Wireline Communications. MWSCAS Eunji Song, Jeonghyu Yang, Seungwook Hong, Jaeduk Han
2022	J	`jnl`	A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids. CoRR Taeho Shin, Dongjun Lee, Dongwhee Kim, Gaeryun Sung, Wookjin Shin, Yunseong Jo, Hyungjoo Park, Jaeduk Han
2022	J	`jnl`	A Discharge-Path-Based Sensing Circuit With OTS Snapback Current Protection for Phase Change Memories. IEEE Access Taeung No, Seonjun Choi, Gaeryun Sung, Seong-Beom Kim, Jaeduk Han, Yun Heub Song
2022	C	`conf`	A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow. ISCAS Zhongkai Wang, Minsoo Choi, John Charles Wright, Kyoungtae Lee, Zhaokai Liu, Bozhi Yin, Jaeduk Han, Sijun Du, Elad Alon
2022	J	`jnl`	An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS. IEEE J. Solid State Circuits Zhongkai Wang, Minsoo Choi, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon
2022	C	`conf`	Energy-Efficient Bus Encoding Techniques for Next-Generation PAM-4 DRAM Interfaces. ICCD Youri Su, Sanghun Lee, Eunji Song, Dongha Kim, Jaeduk Han, Hokeun Kim
2021	—	`conf`	8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS. ISSCC Minsoo Choi, Zhongkai Wang, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Elad Alon
2021	—	`conf`	A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits. ISOCC Taeho Shin, Jaeduk Han
2021	J	`jnl`	Automatic prior selection for image deconvolution: Statistical modeling on natural images. Signal Process. Haegeun Lee, Jaeduk Han, Soonyoung Hong, Moon Gi Kang
2021	—	`conf`	Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology. ISOCC Dongjun Lee, Jaeduk Han
2021	—	`conf`	High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology. ISOCC Gaeryun Sung, Jaeduk Han
2021	J	`jnl`	LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. Jaeduk Han, Woo-Rham Bae, Eric Chang, Zhongkai Wang, Borivoje Nikolic, Elad Alon
2021	A	`conf`	Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies. DATE Youngbog Yoon, Daeyong Han, Shinho Chu, Sangho Lee, Jaeduk Han, Junhyun Chun
2021	J	`jnl`	Thermal Image Restoration Based on LWIR Sensor Statistics. Sensors Jaeduk Han, Haegeun Lee, Moon Gi Kang
2020	J	`jnl`	Canonical Illumination Decomposition and Its Applications. IEEE Trans. Circuits Syst. Video Technol. Jaeduk Han, Soonyoung Hong, Moon Gi Kang
2020	—	`conf`	Computational Color Constancy under Multiple Light Sources. Image Processing: Algorithms and Systems Jaeduk Han, Soonyoung Hong, Moon Gi Kang
2020	—	`conf`	Design Techniques for Robust and Area-efficient Current Sources in Nanometer CMOS Technology. ISOCC Taeung No, Jaeduk Han
2020	J	`jnl`	Multi-Frame Depth Super-Resolution for ToF Sensor With Total Variation Regularized L1 Function. IEEE Access Jonghyun Kim, Jaeduk Han, Moon Gi Kang
2019	—	`conf`	A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit. ESSCIRC Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, Elad Alon
2019	—	`conf`	A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. CICC Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woo-Rham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic, Elad Alon
2019	J	`jnl`	A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits Steven Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic
2019	J	`jnl`	A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. IEEE J. Solid State Circuits Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Orhan Ocal, Paul Rigge, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic
2019	—	`conf`	Design and Automatic Generation of High-Speed Circuits for Wireline Communications. ISOCC Jaeduk Han, Eric Chang, Elad Alon
2019	—	`conf`	Multi-frame super-resolution utilizing spatially adaptive regularization for ToF camera. Image Processing: Algorithms and Systems Haegeun Lee, Jonghyun Kim, Jaeduk Han, Moon Gi Kang
2018	—	`conf`	A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. A-SSCC Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic
2018	—	`conf`	A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET. ESSCIRC Angie Wang, Woo-Rham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolic
2018	J	`jnl`	A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. IEEE Trans. Ind. Electron. Woo-Rham Bae, Haram Ju, Kwanseo Park, Jaeduk Han, Deog-Kyoon Jeong
2018	—	`conf`	An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit. VLSI Circuits Eric Chang, Nathan Narevsky, Jaeduk Han, Elad Alon
2018	—	`conf`	BAG2: A process-portable framework for generator-based AMS circuit design. CICC Eric Chang, Jaeduk Han, Woo-Rham Bae, Zhongkai Wang, Nathan Narevsky, Borivoje Nikolic, Elad Alon
2018	J	`jnl`	Permuted Coordinate-Wise Optimizations Applied to Lp-Regularized Image Deconvolution. IEEE Trans. Image Process. Jaeduk Han, Ki-Sun Song, Jonghyun Kim, Moon Gi Kang
2017	—	`conf`	6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology. ISSCC Jaeduk Han, Yue Lu, Nicholas Sutardja, Elad Alon
2017	—	`conf`	6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. ISSCC Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang
2017	—	`conf`	A 0.37mm A-SSCC Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, Elad Alon, Borivoje Nikolic
2017	J	`jnl`	A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. IEEE J. Solid State Circuits Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang
2017	J	`jnl`	Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology. IEEE J. Solid State Circuits Jaeduk Han, Nicholas Sutardja, Yue Lu, Elad Alon
2017	—	`conf`	Non-blind Image Deconvolution using Sampling without Replacement. Image Processing: Algorithms and Systems Jaeduk Han, Jonghyun Kim, Moon Gi Kang
2016	J	`jnl`	Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology. IEEE J. Solid State Circuits Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon
2015	—	`conf`	A 60Gb/s 173mW receiver frontend in 65nm CMOS technology. VLSIC Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon
2011	—	`conf`	A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface. ISSCC Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Jaeduk Han, Sunkwon Kim, Kyu-Sang Park, Dong-Hyuk Lim, Jung-Hoon Chun, Deog-Kyoon Jeong, Suhwan Kim