Jae Young Hur - RankMe

24 papers Journal 16Unranked 7

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Clustered Page Table Compression for TLB Coalescing. IEEE Access Dai-Duong Tran, Jae Young Hur
2025	J	`jnl`	Contiguity aware TLB prefetching for embedded I/O devices. IEICE Electron. Express Dai-Duong Tran, Jae Young Hur
2025	J	`jnl`	Reinforcement Learning for Resource Allocation in Vehicular Multi-Fog Computing. CoRR Mohammad Hadi Akbarzadeh, Mahmood Ahmadi, Mohammad Saeed Jahangiry, Jae Young Hur
2025	J	`jnl`	TLB Coalescing With Range Compressed Page Table for Embedded I/O Devices. IEEE Access Dai-Duong Tran, Young Seung Kim, Jae Young Hur
2023	J	`jnl`	Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB Coalescing. IEEE Access Dai-Duong Tran, Jae Young Hur
2021	J	`jnl`	Clean-prefetcher: look-ahead prefetching without cache pollution. IEICE Electron. Express Minshin Cho, Jae Young Hur, Wooyoung Jang
2020	J	`jnl`	Near-Threshold L1 Data Cache for Yield Management Under Process Variations. IEEE Access Joonho Kong, Jae Young Hur
2020	J	`jnl`	Page Table Compaction for TLB Coalescing. IEEE Access Jae Young Hur, Joonho Kong
2020	J	`jnl`	TLC STT-MRAM aware LLC for multicore processor. IEICE Electron. Express Taejin Park, Jae Young Hur, Wooyoung Jang
2020	J	`jnl`	Virtual Address Remapping with Configurable Tiles in Image Processing Applications. IEICE Trans. Inf. Syst. Jae Young Hur
2019	J	`jnl`	Adaptive Linear Address Map for Bank Interleaving in DRAMs. IEEE Access Jae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang
2019	J	`jnl`	Block Level TLB Coalescing for Buddy Memory Allocator. IEICE Trans. Inf. Syst. Jae Young Hur
2019	J	`jnl`	Contiguity Representation in Page Table for Memory Management Units. IEEE Trans. Very Large Scale Integr. Syst. Jae Young Hur
2017	—	`conf`	Representing Contiguity in Page Table for Memory Management Units. MCSoC Jae Young Hur
2012	J	`jnl`	Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays. IET Comput. Digit. Tech. Jae Young Hur, Kees Goossens, Lotfi Mhamdi, Muhammad Aqeel Wahlah
2012	J	`jnl`	Customisation of on-chip network interconnects and experiments in field-programmable gate arrays. IET Comput. Digit. Tech. Jae Young Hur, Todor P. Stefanov, Stephan Wong, Kees Goossens
2011	—	`—`	Customizing and hardwiring on-chip interconnects in FPGAs. Jae Young Hur
2010	—	`conf`	A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. SASP Thomas Marconi, Jae Young Hur, Koen Bertels, Georgi Gaydadjiev
2010	J	`jnl`	Design Trade-offs in Customized On-chip Crossbar Schedulers. J. Signal Process. Syst. Jae Young Hur, Stephan Wong, Todor P. Stefanov
2008	—	`conf`	Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. NOCS Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah
2008	—	`conf`	Yeast on a Chip - Single-cell Analyses of MAPK Signaling Pathways in Saccharomyces Cerevisiae using Cell Chips. BIODEVICES (2) Min Cheol Park, Moon Kyu Kwak, Hye Sung Cho, Kahp Y. Suh, Jae Young Hur, Sang-Hyun Park
2007	—	`conf`	Customizing Reconfigurable On-Chip Crossbar Scheduler. ASAP Jae Young Hur, Todor P. Stefanov, Stephan Wong, Stamatis Vassiliadis
2007	—	`conf`	Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs. ARC Jae Young Hur, Stephan Wong, Stamatis Vassiliadis
2007	—	`conf`	Systematic Customization of On-Chip Crossbar Interconnects. ARC Jae Young Hur, Todor P. Stefanov, Stephan Wong, Stamatis Vassiliadis