Jae Hoon Shim

18 papers C 2Journal 10Unranked 6
YearRankTypeTitle / Venue / Authors
2024 — conf
Enhancing Semiconductor X-RAY Images: A Framework Combining Denoising and Super-Resolution Modules With a Novel Dataset.
APSIPA
Jae Hoon Shim, Min Woo Kim, Tae Gyu Lim, Byungseok Min, Sang Hwa Lee, Nam Ik Cho
2023 C conf
An Output-Capacitor-Free Adaptive-Frequency Digital LDO with a 420-mA Load Current and a Fast Settling Time.
ISCAS
Dong-Jick Min, Jun-Gi Lee, Kunhee Cho, Jae Hoon Shim
2023 J jnl
An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jaejin Kim, Gunmo Koo, Seongmin Lee, Jae Hoon Shim, Kunhee Cho
2021 C conf
A Zero-Crossing-Based Integrator with Bidirectional Two-Phase Charging and Selective-Reset Operations for ΔΣ ADCs.
ISCAS
Dong-Jick Min, Jae Hoon Shim
2021 — conf
Lossless Image Compression Based on Image Decomposition and Progressive Prediction Using Convolutional Neural Networks.
APSIPA ASC
Jae Hoon Shim, Hochang Rhee, Yeong Il Jang, Geonsu Lee, Seyun Kim, Nam Ik Cho
2021 — conf
Network Intrusion Detection with Improved Feature Representation.
APSIPA ASC
Geonsu Lee, Hochang Rhee, Jae Hoon Shim, Hyung Il Koo, Nam Ik Cho
2018 J jnl
3D die-stacked DRAM thermal management via task allocation and core pipeline control.
IEICE Electron. Express
Changho Yoon, Jae Hoon Shim, Byungin Moon, Joonho Kong
2018 — conf
A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing Detector.
ICECS
Dong-Jick Min, Sun Youl Choi, Jae Hoon Shim
2018 J jnl
Modified adaptive support weight and disparity search range estimation schemes for stereo matching processors.
J. Supercomput.
Seung-Ho Ok, Jae Hoon Shim, Byungin Moon
2017 J jnl
The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.
Sensors
Seung-Ho Ok, Yong-Hwan Lee, Jae Hoon Shim, Sung Kyu Lim, Byungin Moon
2010 J jnl
Charge Pump circuit with wide range digital leakage current mismatch compensator.
IEICE Electron. Express
Sangjin Byun, Jae Hoon Shim
2006 J jnl
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector.
IEEE J. Solid State Circuits
Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu
2006 — conf
A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector.
ISSCC
Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu
2005 J jnl
A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators.
IEEE J. Solid State Circuits
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2005 J jnl
Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators".
IEEE J. Solid State Circuits
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2005 J jnl
Hybrid ΣΔ modulators with adaptive calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2003 — conf
A hybrid delta-sigma modulator with adaptive calibration.
ISCAS (1)
Jae Hoon Shim, In-Cheol Park, Beomsup Kim
2001 J jnl
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique.
IEEE J. Solid State Circuits
Sung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam, Young Gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim