Jae-Won Nam

27 papers Journal 15Unranked 12
YearRankTypeTitle / Venue / Authors
2025 J jnl
15.4-17 GHz, -187.4 dBc/Hz FoM VCO With Current Reused Coupled Oscillator and Improved Noise Circulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hapsah Aulia Azzahra, Muhammad Fakhri Mauludin, Xi Zhu, Jae-Won Nam, Jusung Kim
2025 — conf
MASH Digital Delta-Sigma Modulators for the CMOS Qubit Controller.
ISVLSI
Hyunyoung Yoo, Muhammad Fakhri Mauludin, Yeonsu Kim, Su-Hyeon Kim, Eun-Ji Yoo, Jae-Yun Park, Jusung Kim, Jae-Won Nam
2024 J jnl
A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control.
IEEE Trans. Circuits Syst. II Express Briefs
Jae-Yun Park, Jae-Won Nam
2024 — conf
AI-Assisted Design Automation of Circular and Asymmetric Inductor in CMOS Technology.
ISOCC
Jin-Won Hyun, Dana Kim, Kyung-Sik Choi, Jae-Won Nam
2023 J jnl
AMS Circuit Design Optimization Technique Based on ANN Regression Model With VAE Structure.
IEEE Access
Jin-Won Hyun, Jae-Won Nam
2023 J jnl
Analysis of Quarter Method Applied ROM-Based DDFS Architecture.
IEEE Access
Jae-Yun Park, Su-Hyeon Kim, Hyunyoung Yoo, Jae-Won Nam
2023 J jnl
High-Speed Light Detection Sensor for Hardware Security in Standard CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Dana Kim, Jong-Phil Hong, Jiwon Lee, Jae-Won Nam
2023 J jnl
Optimizing EV Chargers Location via Integer Programming.
CoRR
Seungmo Kim, Yeonho Jeong, Jae-Won Nam
2023 — conf
Regression Model-based VCO Design Optimization Technique.
ICEIC
Jin-Won Hyun, Jae-Won Nam
2022 J jnl
A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Kyun Cho, Jae-Won Nam, Sang-Won Lee
2022 J jnl
Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique.
IEEE Access
Jae-Won Nam, Ju-Hyeok Ahn, Jong-Phil Hong
2021 — conf
Generative Adversarial Attacks on Fingerprint Recognition Systems.
ICOIN
Hee won Kwon, Jae-Won Nam, Joongheon Kim, Youn Kyu Lee
2021 — conf
HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks.
ASP-DAC
Soowang Park, Jae-Won Nam, Sandeep K. Gupta
2021 — conf
Machine-Learning based Analog and Mixed-signal Circuit Design and Optimization.
ICOIN
Jae-Won Nam, Youn Kyu Lee
2020 J jnl
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer.
IEEE J. Solid State Circuits
Jae-Won Nam, Mike Shuo-Wei Chen
2019 — conf
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS.
CICC
Jae-Won Nam, Mike Shuo-Wei Chen
2018 J jnl
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation.
IEEE J. Solid State Circuits
Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen
2016 — conf
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS.
VLSI Circuits
Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen
2016 J jnl
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jae-Won Nam, Mike Shuo-Wei Chen
2013 — conf
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS.
CICC
Jae-Won Nam, David Chiong, Mike Shuo-Wei Chen
2012 J jnl
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Deuk Jeon, Jae-Won Nam, Kwi-Dong Kim, Tae Moon Roh, Jong-Kee Kwon
2011 J jnl
A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications.
Microelectron. J.
Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon
2011 — conf
A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS.
ISOCC
Jae-Won Nam, Young-Deuk Jeon, Seok-Ju Yun, Tae Moon Roh, Jong-Kee Kwon
2011 J jnl
A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique.
Microelectron. J.
Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Jong-Kee Kwon
2010 J jnl
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon
2010 — conf
A 9.15mW 0.22mm
CICC
Young-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam, Kwi-Dong Kim, Woo-Yol Lee, Kuk-Tae Hong, Jong-Kee Kwon
2009 — conf
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS.
ESSCIRC
Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Sang-Gug Lee, Jong-Kee Kwon