Jae-sun Seo - RankMe

203 papers A* 12A 30B 8C 11Misc 6Journal 75Unranked 60

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	vFPGA: Towards Sub-µs Reconfiguration via 3D FPGA and Packaging Co-Design. FPGA Nikhil K. Cherukuri, Sharad Nag, Pragnya Sudershan Nalla, Ashish K. Kola, Chetan S. Gadireddi, Kevin Dai, Jae-sun Seo, Zhenman Fang, Jeff Zhang, Yu Cao
2025	—	`conf`	A 28nm 20.9-137.2 TOPS/W Output-Stationary SRAM Compute-in-Memory Macro Featuring Dynamic Look-ahead Zero Weight Skipping and Runtime Partial Sum Quantization. CICC Xiaofeng Hu, HanGyeol Mun, Jian Meng, Yuan Liao, Amitesh Sridharan, Jae-sun Seo
2025	J	`jnl`	Accelerating Diffusion Language Model Inference via Efficient KV Caching and Guided Diffusion. CoRR Zhanqiu Hu, Jian Meng, Yash Akhauri, Mohamed S. Abdelfattah, Jae-sun Seo, Zhiru Zhang, Udit Gupta
2025	A	`conf`	CTDM: Resource-Efficient FPGA-Accelerated Simulation of Large-Scale NPU Designs. ICCAD Hyunje Jo, Han-Sok Suh, Hyun-Seok Heo, Jinseok Kim, Hyunsung Kim, Boeui Hong, Jungju Oh, Sunghyun Park, Jinwook Oh, Sunghwan Jo, Kangwook Lee, Jae-sun Seo
2025	A*	`conf`	Closest Neighbors are Harmful for Lightweight Masked Auto-encoders. CVPR Jian Meng, Ahmed Hassan, Li Yang, Deliang Fan, Jinwoo Shin, Jae-sun Seo
2025	—	`conf`	H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications (Abstract). HOPC@SPAA Yiwei Zhao, Jinhui Chen, Sai Qian Zhang, Syed Shakib Sarwar, Kleber Hugo Stangherlin, Jorge Tomás Gómez, Jae-sun Seo, Barbara De Salvo, Chiao Liu, Phillip B. Gibbons, Ziyun Li
2025	—	`conf`	H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications. ASP-DAC Yiwei Zhao, Jinhui Chen, Sai Qian Zhang, Syed Shakib Sarwar, Kleber Hugo Stangherlin, Jorge Tomás Gómez, Jae-sun Seo, Barbara De Salvo, Chiao Liu, Phillip B. Gibbons, Ziyun Li
2025	J	`jnl`	HISIM: Analytical Performance Modeling and Design Space Exploration of 2.5D/3D Integration for AI Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhenyu Wang, Pragnya Sudershan Nalla, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-sun Seo, Vidya A. Chhabria, Jeff Zhang, Chaitali Chakrabarti, Ümit Y. Ogras, Yu Cao
2025	A	`conf`	Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference. ISLPED Chun-Ting Chen, HanGyeol Mun, Jian Meng, Mohamed S. Abdelfattah, Jae-sun Seo
2025	J	`jnl`	Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference. CoRR Chun-Ting Chen, HanGyeol Mun, Jian Meng, Mohamed S. Abdelfattah, Jae-sun Seo
2025	C	`conf`	Low-Precision Normalization Algorithm and Accelerator for Neural Network Training. ISCAS Han-Sok Suh, Jian Meng, Jae-sun Seo
2025	Misc	`conf`	Quant-NeRF: Efficient End-to-End Quantization of Neural Radiance Fields with Low-Precision 3D Gaussian Representation. ICASSP Ahmed Hasssan, Anupreetham Anupreetham, Jian Meng, Jae-sun Seo
2025	A*	`conf`	Skrr: Skip and Re-use Text Encoder Layers for Memory Efficient Text-to-Image Generation. ICML Hoigi Seo, Wongi Jeong, Jae-sun Seo, Se Young Chun
2025	J	`jnl`	Skrr: Skip and Re-use Text Encoder Layers for Memory Efficient Text-to-Image Generation. CoRR Hoigi Seo, Wongi Jeong, Jae-sun Seo, Se Young Chun
2024	A	`conf`	3D IC Architecture Evaluation and Optimization with Digital Compute-in-Memory Designs. ISLPED Hyung Joon Byun, Udit Gupta, Jae-sun Seo
2024	A	`conf`	A 28nm Scalable and Flexible Accelerator for Sparse Transformer Models. ISLPED Yuan Liao, Jian Meng, Jae-sun Seo
2024	J	`jnl`	A 65-nm RRAM Compute-in-Memory Macro for Genome Processing. IEEE J. Solid State Circuits Fan Zhang, Amitesh Sridharan, Wangxin He, Injune Yeo, Maximilian Liehr, Wei Zhang, Nathaniel C. Cady, Yu Cao, Jae-sun Seo, Deliang Fan
2024	J	`jnl`	A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. IEEE Micro Huseyin Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigné
2024	A*	`conf`	BBS: Bi-Directional Bit-Level Sparsity for Deep Learning Acceleration. MICRO Yuzong Chen, Jian Meng, Jae-sun Seo, Mohamed S. Abdelfattah
2024	J	`jnl`	BBS: Bi-directional Bit-level Sparsity for Deep Learning Acceleration. CoRR Yuzong Chen, Jian Meng, Jae-sun Seo, Mohamed S. Abdelfattah
2024	J	`jnl`	Context-Aware Token Selection and Packing for Enhanced Vision Transformer. CoRR Tianyi Zhang, Baoxin Li, Jae-sun Seo, Yu Cap
2024	B	`conf`	Exploiting 2.5D/3D Heterogeneous Integration for AI Computing. ASPDAC Zhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Yaotian Liu, Jae-sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Jeff Zhang, Yu Cao
2024	J	`jnl`	Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Mike Shuo-Wei Chen, Visvesh S. Sathe, Massimo Alioto, Jae-sun Seo, Hidehiro Shiga
2024	J	`jnl`	High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. ACM Trans. Reconfigurable Technol. Syst. Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2024	—	`conf`	IM-SNN: Memory-Efficient Spiking Neural Network with Low-Precision Membrane Potentials and Weights. ICONS Ahmed Hasssan, Jian Meng, Anupreetham Anupreetham, Jae-sun Seo
2024	—	`ch.`	In-Memory Computing for AI Accelerators: Challenges and Solutions. Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Hardware Architectures Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2024	J	`jnl`	MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks. IEEE J. Solid State Circuits Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok
2024	J	`jnl`	Neural Architecture Search of Hybrid Models for NPU-CIM Heterogeneous AR/VR Devices. CoRR Yiwei Zhao, Ziyun Li, Win-San Khwa, Xiaoyu Sun, Sai Qian Zhang, Syed Shakib Sarwar, Kleber Hugo Stangherlin, Yi-Lun Lu, Jorge Tomás Gómez, Jae-sun Seo, Phillip B. Gibbons, Barbara De Salvo, Chiao Liu
2024	—	`conf`	POCA: Post-training Quantization with Temporal Alignment for Codec Avatars. ECCV (40) Jian Meng, Yuecheng Li, Chenghui Li, Syed Shakib Sarwar, Dilin Wang, Jae-sun Seo
2024	A	`conf`	Patch-based Selection and Refinement for Early Object Detection. WACV Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2024	—	`conf`	SHIFFT: A Scalable Hybrid In-Memory Computing FFT Accelerator. ISVLSI Pragnya Sudershan Nalla, Zhenyu Wang, Sapan Agarwal, T. Patrick Xiao, Christopher H. Bennett, Matthew J. Marinella, Jae-sun Seo, Yu Cao
2024	—	`conf`	SP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN Workloads. CICC Amitesh Sridharan, Fan Zhang, Jae-sun Seo, Deliang Fan
2024	B	`conf`	Spiking Neural Network with Learnable Threshold for Event-based Classification and Object Detection. IJCNN Ahmed Hasssan, Jian Meng, Jae-sun Seo
2024	—	`conf`	Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design. MLSys Jian Meng, Yuan Liao, Anupreetham Anupreetham, Ahmed Hassan, Shixing Yu, Han-Sok Suh, Xiaofeng Hu, Jae-sun Seo
2024	J	`jnl`	Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design. CoRR Jian Meng, Yuan Liao, Anupreetham Anupreetham, Ahmed Hassan, Shixing Yu, Han-Sok Suh, Xiaofeng Hu, Jae-sun Seo
2024	A*	`conf`	Transformer-Based Selective Super-resolution for Efficient Image Refinement. AAAI Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2023	—	`conf`	3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression. A-SSCC Gokul Krishnan, Gopikrishnan Raveendran Nair, Jonghyun Oh, Anupreetham Anupreetham, Pragnya Sudershan Nalla, Ahmed Hassan, Injune Yeo, Kishore Kasichainula, Jae-sun Seo, Mingoo Seok, Yu Cao
2023	—	`conf`	A 138-TOPS/W Delta-Sigma Modulator-Based Variable- Resolution Activation in-Memory Computing Macro. CICC Vasundhara Damodaran, Ziyu Liu, Jae-sun Seo, Arindam Sanyal
2023	J	`jnl`	A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. IEEE J. Solid State Circuits Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo
2023	—	`conf`	A 65nm RRAM Compute-in-Memory Macro for Genome Sequencing Alignment. ESSCIRC Fan Zhang, Wangxin He, Injune Yeo, Maximilian Liehr, Nathaniel C. Cady, Yu Cao, Jae-sun Seo, Deliang Fan
2023	—	`conf`	A 92 F CICC Injune Yeo, Dong-Woo Jee, Jae-sun Seo
2023	—	`conf`	A Delta-Sigma Based SRAM Compute-in-Memory Macro for Human Activity Recognition. BioCAS Vasundhara Damodaran, Ziyu Liu, Jae-sun Seo, Arindam Sanyal
2023	—	`conf`	A Time-Memory-based CMOS Vision Sensor with In-Pixel Temporal Derivative Computing for Multi-Mode Image Processing. ESSCIRC Dong-Woo Jee, Seong-Min Ko, Kishore Kasichainula, Injune Yeo, Yu Cao, Jae-sun Seo
2023	A*	`conf`	Advances and Trends on On-Chip Compute-in-Memory Macros and Accelerators. DAC Jae-sun Seo
2023	J	`jnl`	Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA. ACM Trans. Reconfigurable Technol. Syst. Han-Sok Suh, Jian Meng, Ty Nguyen, Vijay Kumar, Yu Cao, Jae-sun Seo
2023	—	`conf`	Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling. ASICON Zhenyu Wang, Jingbo Sun, A. Alper Goksoy, Sumit K. Mandal, Jae-sun Seo, Chaitali Chakrabarti, Ümit Y. Ogras, Vidya A. Chhabria, Yu Cao
2023	—	`conf`	FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro. ESSCIRC Jyotishman Saikia, Amitesh Sridharan, Injune Yeo, Shreyas K. Venkataramanaiah, Deliang Fan, Jae-sun Seo
2023	A	`conf`	FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix. DATE Gopikrishnan Raveendran Nair, Han-Sok Suh, Mahantesh Halappanavar, Frank Liu, Jae-sun Seo, Yu Cao
2023	C	`conf`	Improving the Efficiency of CMOS Image Sensors through In-Sensor Selective Attention. ISCAS Tianyi Zhang, Kishore Kasichainula, Dong-Woo Jee, Injune Yeo, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2023	J	`jnl`	NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking. CoRR Jason Yik, Soikat Hasan Ahmed, Zergham Ahmed, Brian Anderson, Andreas G. Andreou, Chiara Bartolozzi, Arindam Basu, Douwe den Blanken, Petrut Bogdan, Sander M. Bohté, Younes Bouhadjar, Sonia M. Buckley, Gert Cauwenberghs, Federico Corradi, Guido de Croon, Andreea Danielescu, Anurag Reddy Daram, Mike Davies, Yigit Demirag, Jason Eshraghian, Jeremy Forest, Steve B. Furber, P. Michael Furlong, Aditya Gilra, Giacomo Indiveri, Siddharth Joshi, Vedant Karia, Lyes Khacef, James C. Knight, Laura Kriener, Rajkumar Kubendran, Dhireesha Kudithipudi, Gregor Lenz, Rajit Manohar, Christian Mayr, Konstantinos P. Michmizos, Dylan R. Muir, Emre Neftci, Thomas Nowotny, Fabrizio Ottati, Ayça Özcelikkale, Noah Pacik-Nelson, Priyadarshini Panda, Pao-Sheng Sun, Melika Payvand, Christian Pehle, Mihai A. Petrovici, Christoph Posch, Alpha Renner, Yulia Sandamirskaya, Clemens JS Schaefer, André van Schaik, Johannes Schemmel, Catherine D. Schuman, Jae-sun Seo, Sumit Bam Shrestha, Manolis Sifalakis, Amos Sironi, Kenneth Michael Stewart, Terrence C. Stewart, Philipp Stratmann, Guangzhi Tang, Jonathan Timcheck, Marian Verhelst, Craig M. Vineyard, Bernhard Vogginger, Amirreza Yousefzadeh, Biyan Zhou, Fatima Tuz Zohora, Charlotte Frenkel, Vijay Janapa Reddi
2023	J	`jnl`	PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference. IEEE J. Solid State Circuits Bo Zhang, Shihui Yin, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok
2023	A	`conf`	PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration. DATE Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo
2023	J	`jnl`	Patch-based Selection and Refinement for Early Object Detection. CoRR Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2023	A*	`conf`	Slimmed Asymmetrical Contrastive Learning and Cross Distillation for Lightweight Model Training. NeurIPS Jian Meng, Li Yang, Kyungmin Lee, Jinwoo Shin, Deliang Fan, Jae-sun Seo
2023	J	`jnl`	Transformer-based Selective Super-Resolution for Efficient Image Refinement. CoRR Tianyi Zhang, Kishore Kasichainula, Yaoxin Zhuo, Baoxin Li, Jae-sun Seo, Yu Cao
2022	—	`conf`	A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm. ESSCIRC Amitesh Sridharan, Shaahin Angizi, Sai Kiran Cherupally, Fan Zhang, Jae-sun Seo, Deliang Fan
2022	—	`conf`	A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. CICC Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok
2022	—	`conf`	A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. ESSCIRC Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo
2022	A	`conf`	Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture. ICCAD Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2022	A*	`conf`	Contrastive Dual Gating: Learning Sparse Features With Contrastive Learning. CVPR Jian Meng, Li Yang, Jinwoo Shin, Deliang Fan, Jae-sun Seo
2022	J	`jnl`	Efficient continual learning at the edge with progressive segmented training. Neuromorph. Comput. Eng. Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Han-Sok Suh, Shihui Yin, Gokul Krishnan, Frank Liu, Jae-sun Seo, Yu Cao
2022	A*	`conf`	Get More at Once: Alternating Sparse Training with Gradient Correction. NeurIPS Li Yang, Jian Meng, Jae-sun Seo, Deliang Fan
2022	J	`jnl`	Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang, Jian Meng, Maximilian Liehr, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-sun Seo, Yu Cao
2022	J	`jnl`	Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks. ACM J. Emerg. Technol. Comput. Syst. Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2022	J	`jnl`	Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection. IEEE Des. Test Sai Kiran Cherupally, Jian Meng, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, Jae-sun Seo
2022	—	`conf`	Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference. IRPS Jian Meng, Injune Yeo, Wonbo Shim, Li Yang, Deliang Fan, Shimeng Yu, Jae-sun Seo
2022	—	`conf`	Spatial-temporal Data Compression of Dynamic Vision Sensor Output with High Pixel-level Saliency using Low-precision Sparse Autoencoder. IEEECONF Ahmed Hassan, Jian Meng, Yu Cao, Jae-sun Seo
2022	J	`jnl`	Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference. IEEE Micro Jian Meng, Wonbo Shim, Li Yang, Injune Yeo, Deliang Fan, Shimeng Yu, Jae-sun Seo
2022	—	`conf`	XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption. ASP-DAC Fan Zhang, Li Yang, Jian Meng, Yu Kevin Cao, Jae-sun Seo, Deliang Fan
2022	A*	`conf`	XMA: a crossbar-aware multi-task adaption framework via shift-based mask learning method. DAC Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Kevin Cao, Deliang Fan
2022	A	`conf`	XST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning. DATE Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Cao, Deliang Fan
2021	J	`jnl`	A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference. IEEE J. Emerg. Sel. Topics Circuits Syst. Arnab Neelim Mazumder, Jian Meng, Hasib-Al Rashid, Utteja Kallakuri, Xin Zhang, Jae-sun Seo, Tinoosh Mohsenin
2021	—	`conf`	Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA. FPT Han-Sok Suh, Jian Meng, Ty Nguyen, Shreyas K. Venkataramanaiah, Vijay Kumar, Yu Cao, Jae-sun Seo
2021	J	`jnl`	An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access. IEEE J. Solid State Circuits Minkyu Kim, Jae-sun Seo
2021	—	`conf`	Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing. IRPS Wangxin He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, Jae-sun Seo
2021	B	`conf`	End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2021	B	`conf`	FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access. FPL Jian Meng, Shreyas Kolala Venkataramanaiah, Chuteng Zhou, Patrick Hansen, Paul N. Whatmough, Jae-sun Seo
2021	J	`jnl`	Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence. IEEE J. Emerg. Sel. Topics Circuits Syst. Tinoosh Mohsenin, Inna Partin-Vaisband, Houman Homayoun, Jae-sun Seo, Xin Zhang
2021	C	`conf`	Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks. ISCAS Vinay Joshi, Wangxin He, Jae-sun Seo, Bipin Rajendran
2021	J	`jnl`	Hybrid In-memory Computing Architecture for the Training of Deep Neural Networks. CoRR Vinay Joshi, Wangxin He, Jae-sun Seo, Bipin Rajendran
2021	—	`conf`	Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine. IRPS Wonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, Shimeng Yu
2021	J	`jnl`	Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks. CoRR Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2021	A*	`conf`	Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. DAC Sai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, Jae-sun Seo
2021	A	`conf`	Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. DATE Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-sun Seo
2021	—	`conf`	PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. VLSI Circuits Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo
2021	J	`jnl`	RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy. CoRR Adnan Siraj Rakin, Li Yang, Jingtao Li, Fan Yao, Chaitali Chakrabarti, Yu Cao, Jae-sun Seo, Deliang Fan
2021	J	`jnl`	SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. CoRR Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2021	J	`jnl`	SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks. ACM Trans. Embed. Comput. Syst. Gokul Krishnan, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2021	J	`jnl`	Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, Jae-sun Seo
2021	—	`conf`	System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration. ASICON Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2020	J	`jnl`	A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs. IEEE J. Emerg. Sel. Topics Circuits Syst. Sumit K. Mandal, Gokul Krishnan, Chaitali Chakrabarti, Jae-sun Seo, Yu Cao, Ümit Y. Ogras
2020	J	`jnl`	A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation. IEEE J. Solid State Circuits Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, ChiSung Bae, Sang Joon Kim, Jae-sun Seo
2020	C	`conf`	A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out. ISCAS Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Mark S. Rodder, Jae-sun Seo, Shimeng Yu
2020	J	`jnl`	An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition. IEEE J. Solid State Circuits Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo
2020	A	`conf`	An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. DATE Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran
2020	J	`jnl`	Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2020	J	`jnl`	Benchmarking TinyML Systems: Challenges and Direction. CoRR Colby R. Banbury, Vijay Janapa Reddi, Max Lam, William Fu, Amin Fazel, Jeremy Holleman, Xinyuan Huang, Robert Hurtado, David Kanter, Anton Lokhmotov, David A. Patterson, Danilo Pau, Jae-sun Seo, Jeff Sieracki, Urmish Thakker, Marian Verhelst, Poonam Yadav
2020	J	`jnl`	C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism. IEEE J. Solid State Circuits Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok
2020	A	`conf`	Compressing LSTM Networks with Hierarchical Coarse-Grain Sparsity. INTERSPEECH Deepak Kadetotad, Jian Meng, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo
2020	—	`conf`	Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access. CICC Minkyu Kim, Jae-sun Seo
2020	—	`conf`	Deep Neural Network Training Accelerator Designs in ASIC and FPGA. ISOCC Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao, Jae-sun Seo
2020	J	`jnl`	ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression. IEEE Trans. Biomed. Circuits Syst. Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Gaurav Srivastava, ChiSung Bae, Sang Joon Kim, Jae-sun Seo
2020	A*	`conf`	Efficient and Modularized Training on FPGA for Real-time Applications. IJCAI Shreyas Kolala Venkataramanaiah, Xiaocong Du, Zheng Li, Shihui Yin, Yu Cao, Jae-sun Seo
2020	A	`conf`	FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. ICCAD Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2020	—	`conf`	Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction. IRPS Wonbo Shim, Yandong Luo, Jae-sun Seo, Shimeng Yu
2020	J	`jnl`	Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs. IEEE Des. Test Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
2020	—	`conf`	Noise-based Selection of Robust Inherited Model for Accurate Continual Learning. CVPR Workshops Xiaocong Du, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao
2020	B	`conf`	Online Knowledge Acquisition with the Selective Inherited Model. IJCNN Xiaocong Du, Shreyas Kolala Venkataramanaiah, Zheng Li, Jae-sun Seo, Frank Liu, Yu Cao
2020	J	`jnl`	Performance Modeling for CNN Inference Accelerators on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2020	—	`conf`	Regulation Control Design Techniques for Integrated Switched Capacitor Voltage Regulators. MWSCAS Usama Awais, Jae-sun Seo
2020	J	`jnl`	Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Shihui Yin, Zhewei Jiang, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-sun Seo
2020	J	`jnl`	XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks. IEEE J. Solid State Circuits Shihui Yin, Zhewei Jiang, Jae-sun Seo, Mingoo Seok
2019	J	`jnl`	A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring. IEEE J. Solid State Circuits Shihui Yin, Minkyu Kim, Deepak Kadetotad, Yang Liu, ChiSung Bae, Sang Joon Kim, Yu Cao, Jae-sun Seo
2019	—	`conf`	A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip. ESSCIRC Deepak Kadetotad, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo
2019	J	`jnl`	A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Luning Wei, Xiaofei He, Yu Cao, Jae-sun Seo
2019	—	`conf`	A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation. A-SSCC Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, ChiSung Bae, Sang Joon Kim, Jae-sun Seo
2019	B	`conf`	Automatic Compiler Based FPGA Accelerator for CNN Training. FPL Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2019	J	`jnl`	Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2019	—	`conf`	C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing. ESSCIRC Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok
2019	—	`conf`	Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks. VLSI-DAT Mingoo Seok, Minhao Yang, Zhewei Jiang, Aurel A. Lazar, Jae-sun Seo
2019	J	`jnl`	Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview. IEEE J. Emerg. Sel. Topics Circuits Syst. Chia-Yu Chen, Boris Murmann, Jae-sun Seo, Hoi-Jun Yoo
2019	C	`conf`	ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression. ISCAS Sai Kiran Cherupally, Gaurav Srivastava, Shihui Yin, Deepak Kadetotad, ChiSung Bae, Sang Joon Kim, Jae-sun Seo
2019	J	`jnl`	FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning. CoRR Paul N. Whatmough, Chuteng Zhou, Patrick Hansen, Shreyas K. Venkataramanaiah, Jae-sun Seo, Matthew Mattina
2019	—	`conf`	FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning. SysML Paul N. Whatmough, Chuteng Zhou, Patrick Hansen, Shreyas K. Venkataramanaiah, Jae-sun Seo, Matthew Mattina
2019	J	`jnl`	Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning. ACM J. Emerg. Technol. Comput. Syst. Jae-sun Seo, Yu Cao, Xin Li, Paul N. Whatmough
2019	J	`jnl`	Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2). ACM J. Emerg. Technol. Comput. Syst. Jae-sun Seo, Yu Cao, Xin Li, Paul N. Whatmough
2019	J	`jnl`	High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS. CoRR Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo
2019	—	`conf`	Inference engine benchmarking across technological platforms from CMOS to RRAM. MEMSYS Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu
2019	Misc	`conf`	Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks. ICASSP Gaurav Srivastava, Deepak Kadetotad, Shihui Yin, Visar Berisha, Chaitali Chakrabarti, Jae-sun Seo
2019	A	`conf`	K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. ISLPED Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo
2019	J	`jnl`	Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. IEEE Micro Shihui Yin, Jae-sun Seo, Yulhwa Kim, Xu Han, Hugh J. Barnaby, Shimeng Yu, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae-Joon Kim
2019	—	`conf`	Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays. ICECS Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Shihui Yin, Jae-sun Seo, Bipin Rajendran
2019	Misc	`conf`	Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration. ACSSC Zhewei Jiang, Shihui Yin, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-sun Seo
2019	—	`conf`	XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism. ACM Great Lakes Symposium on VLSI Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok
2018	J	`jnl`	A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware. J. Signal Process. Syst. Mohit Shah, Sairam Arunachalam, Jingcheng Wang, David T. Blaauw, Dennis Sylvester, Hun-Seok Kim, Jae-sun Seo, Chaitali Chakrabarti
2018	—	`conf`	A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks. SiPS Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, Chaitali Chakrabarti
2018	J	`jnl`	ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018	A	`conf`	Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018	—	`conf`	Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu
2018	J	`jnl`	Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms. IEEE J. Emerg. Sel. Topics Circuits Syst. Arindam Basu, Meng-Fan Chang, Elisabetta Chicca, Tanay Karnik, Hai Helen Li, Jae-sun Seo
2018	J	`jnl`	Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning. ACM J. Emerg. Technol. Comput. Syst. Yu Cao, Xin Li, Jae-sun Seo, Ganesh Dasika
2018	J	`jnl`	Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain. CoRR Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings
2018	—	`conf`	Low Power and Trusted Machine Learning. ACM Great Lakes Symposium on VLSI Avesta Sasan, Qi Zhu, Yanzhi Wang, Jae-sun Seo, Tinoosh Mohsenin
2018	J	`jnl`	Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions. IEEE J. Emerg. Sel. Topics Circuits Syst. Arindam Basu, Jyotibdha Acharya, Tanay Karnik, Huichu Liu, Hai Helen Li, Jae-sun Seo, Chang Song
2018	J	`jnl`	Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression. CoRR Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo
2018	J	`jnl`	Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018	J	`jnl`	Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition. ACM J. Emerg. Technol. Comput. Syst. Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim
2018	J	`jnl`	Process Scalability of Pulse-Based Circuits for Analog Image Convolution. IEEE Trans. Circuits Syst. I Regul. Pap. Robert D'Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao Huang, Nhut Tran, Armand Chery, Jae-sun Seo, Yu Cao, Dorothy C. Poppe, Sameer R. Sonkusale
2018	Misc	`conf`	Towards a Wearable Cough Detector Based on Neural Networks. ICASSP Prad Kadambi, Abinash Mohanty, Hao Ren, Jaclyn Smith, Kevin McGuinnes, Kimberly Holt, Armin Furtwaengler, Roberto Slepetys, Zheng Yang, Jae-sun Seo, Junseok Chae, Yu Cao, Visar Berisha
2018	A	`conf`	XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks. DATE Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu
2017	—	`conf`	A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
2017	C	`conf`	A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
2017	J	`jnl`	Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo
2017	—	`conf`	Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo
2017	B	`conf`	An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	—	`conf`	Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs. IWANN (2) Ricardo Tapiador-Morales, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim, Deepak Kadetotad, Jae-sun Seo
2017	—	`conf`	Designing ECG-based physical unclonable function for security of wearable devices. EMBC Shihui Yin, ChiSung Bae, Sang Joon Kim, Jae-sun Seo
2017	C	`conf`	End-to-end scalable FPGA accelerator for deep residual networks. ISCAS Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	A	`conf`	Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators. DATE Xiaoyang Mi, Hesam Fathi Moghadam, Jae-sun Seo
2017	J	`jnl`	Improving efficiency in sparse learning with the feedforward inhibitory motif. Neurocomputing Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, Yu Cao
2017	—	`conf`	Low-power neuromorphic speech recognition engine with coarse-grain sparsity. ASP-DAC Shunti Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, Chaitali Chakrabarti, Jae-sun Seo
2017	Misc	`conf`	Minimizing area and energy of deep learning hardware design using collective low precision and structured compression. ACSSC Shihui Yin, Gaurav Srivastava, Shreyas K. Venkataramanaiah, Chaitali Chakrabarti, Visar Berisha, Jae-sun Seo
2017	A	`conf`	Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. ISLPED Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, Sung Kyu Lim
2017	A	`conf`	Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	J	`jnl`	Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities. IEEE J. Solid State Circuits Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, Mingoo Seok
2016	J	`jnl`	A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering. IEEE J. Solid State Circuits Suyoung Bang, Jae-sun Seo, Leland Chang, David T. Blaauw, Dennis Sylvester
2016	A*	`conf`	Bi-Level Rare Temporal Pattern Detection. ICDM Dawei Zhou, Jingrui He, Yu Cao, Jae-sun Seo
2016	A	`conf`	Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. ICCAD Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu
2016	J	`jnl`	Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs. CoRR Ricardo Tapiador, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim, Deepak Kadetotad, Jae-sun Seo
2016	A	`conf`	Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications. ICCAD Deepak Kadetotad, Sairam Arunachalam, Chaitali Chakrabarti, Jae-sun Seo
2016	C	`conf`	High-performance face detection with CPU-FPGA acceleration. ISCAS Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2016	Misc	`conf`	Ranking the parameters of deep neural networks using the fisher information. ICASSP Ming Tu, Visar Berisha, Martin Woolf, Jae-sun Seo, Yu Cao
2016	J	`jnl`	Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula
2016	—	`conf`	Reducing the Model Order of Deep Neural Networks Using Information Theory. ISVLSI Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo
2016	J	`jnl`	Reducing the Model Order of Deep Neural Networks Using Information Theory. CoRR Ming Tu, Visar Berisha, Yu Cao, Jae-sun Seo
2016	B	`conf`	Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
2016	A	`conf`	Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2016	—	`conf`	Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability. A-SSCC Jiangyi Li, Jae-sun Seo, Ioannis Kymissis, Mingoo Seok
2015	—	`conf`	A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple. VLSIC Suyoung Bang, Jae-sun Seo, Inhee Lee, Seokhyeon Jeong, Nathaniel Ross Pinckney, David T. Blaauw, Dennis Sylvester, Leland Chang
2015	A	`conf`	A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems. ISLPED Beinuo Zhang, Zhewei Jiang, Qi Wang, Jae-sun Seo, Mingoo Seok
2015	A	`conf`	Analysis and optimization of CMOS switched-capacitor converters. ISLPED Visvesh S. Sathe, Jae-sun Seo
2015	C	`conf`	Digital CMOS neuromorphic processor design featuring unsupervised online learning. VLSI-SoC Jae-sun Seo, Mingoo Seok
2015	—	`conf`	Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. CICC Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula
2015	C	`conf`	Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. ICCD Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
2015	A	`conf`	Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS. ISLPED Xiaoyang Mi, Debashis Mandal, Visvesh S. Sathe, Bertan Bakkaloglu, Jae-sun Seo
2015	A	`conf`	Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2015	J	`jnl`	Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2015	A	`conf`	Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2014	—	`conf`	Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2014	—	`conf`	Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao
2013	—	`conf`	A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. ISSCC Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman
2011	—	`conf`	A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. CICC Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman
2011	J	`jnl`	A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect. IEEE Trans. Very Large Scale Integr. Syst. Jae-sun Seo, Himanshu Kaul, Ram Krishnamurthy, Dennis Sylvester, David T. Blaauw
2011	J	`jnl`	Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS. IEEE J. Solid State Circuits Jae-sun Seo, David T. Blaauw, Dennis Sylvester
2010	—	`conf`	High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. ISSCC Jae-sun Seo, Ron Ho, Jon K. Lexau, Michael Dayringer, Dennis Sylvester, David T. Blaauw
2010	—	`conf`	In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter. ISSCC David Fick, Nurrachman Liu, Zhiyoong Foo, Matthew Fojtik, Jae-sun Seo, Dennis Sylvester, David T. Blaauw
2009	J	`jnl`	A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. IEEE J. Solid State Circuits Jongwoo Lee, Joshua Jaeyoung Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn
2008	C	`conf`	A robust alternate repeater technique for high performance busses in the multi-core era. ISCAS Himanshu Kaul, Jae-sun Seo, Mark A. Anders, Dennis Sylvester, Ram Krishnamurthy
2008	A	`conf`	On the decreasing significance of large standard cells in technology mapping. ICCAD Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David T. Blaauw
2008	—	`conf`	Robust ultra-low voltage ROM design. CICC Mingoo Seok, Scott Hanson, Jae-sun Seo, Dennis Sylvester, David T. Blaauw
2008	J	`jnl`	Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. IEEE Trans. Very Large Scale Integr. Syst. Prashant Singh, Jae-sun Seo, David T. Blaauw, Dennis Sylvester
2007	A	`conf`	A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy
2007	—	`conf`	Self-Time Regenerators for High-Speed and Low-Power Interconnect. ISQED Jae-sun Seo, Prashant Singh, Dennis Sylvester, David T. Blaauw