Jae-Seok Yang - RankMe

14 papers A* 2A 4Journal 2Unranked 6

Year	Rank	Type	Title / Venue / Authors
2013	J	`jnl`	Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
2012	A	`conf`	Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). ICCAD Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan
2012	—	`conf`	Design for manufacturability and reliability for TSV-based 3D ICs. ASP-DAC David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang
2011	A	`conf`	Chemical-mechanical polishing aware application-specific 3D NoC design. ICCAD Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan
2011	A*	`conf`	Layout aware line-edge roughness modeling and poly optimization for leakage minimization. DAC Yongchan Ban, Jae-Seok Yang
2011	—	`conf`	Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan
2010	—	`conf`	A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. ASP-DAC Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan
2010	J	`jnl`	Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kun Yuan, Jae-Seok Yang, David Z. Pan
2010	A	`conf`	Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
2010	A*	`conf`	TSV stress aware timing analysis with applications to 3D-IC layout optimization. DAC Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan
2009	—	`conf`	Double patterning layout decomposition for simultaneous conflict and stitch minimization. ISPD Kun Yuan, Jae-Seok Yang, David Z. Pan
2008	—	`conf`	Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner. ISQED Jae-Seok Yang, Andrew R. Neureuther
2008	A	`conf`	Overlay aware interconnect and timing variation modeling for double patterning technology. ICCAD Jae-Seok Yang, David Z. Pan
2003	—	`conf`	Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis. ISQED Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, Jeong-Taek Kong