Jae-Joon Kim - RankMe

127 papers A* 19A 27C 2Misc 3Journal 54Unranked 21

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	LRAgent: Efficient KV Cache Sharing for Multi-LoRA LLM Agents. CoRR Hyesung Jeon, Hyeongju Ha, Jae-Joon Kim
2026	J	`jnl`	RelayGen: Intra-Generation Model Switching for Efficient Reasoning. CoRR Jiwon Song, Yoongon Kim, Jae-Joon Kim
2026	J	`jnl`	Token Sparse Attention: Efficient Long-Context Inference with Interleaved Token Selection. CoRR Dongwon Jo, Beomseok Kang, Jiwon Song, Jae-Joon Kim
2025	A	`conf`	An eDRAM Digital In-Memory Neural Network Accelerator for High-Throughput and Extended Data Retention Time. DATE Inhwan Lee, Jehun Lee, Jaeyong Jang, Jae-Joon Kim
2025	A	`conf`	COMPASS: A Compiler Framework for Resource-Constrained Crossbar-Array Based In-Memory Deep Learning Accelerators. DATE Jihoon Park, Jeongin Choe, Dohyun Kim, Jae-Joon Kim
2025	J	`jnl`	COMPASS: A Compiler Framework for Resource-Constrained Crossbar-Array Based In-Memory Deep Learning Accelerators. CoRR Jihoon Park, Jeongin Choe, Dohyun Kim, Jae-Joon Kim
2025	A	`conf`	Compute-in-Memory Array Design Using Stacked Hybrid IGZO/Si eDRAM cells. DATE Munhyeon Kim, Yulhwa Kim, Jae-Joon Kim
2025	A*	`conf`	CrossBit: Bitwise Computing in NAND Flash Memory with Inter-Bitline Data Communication. MICRO HyunJin Kim, Seunghwan Song, Sukhyun Choi, Jeongin Choe, SangHyeok Han, Jisung Park, Jinho Lee, Jae-Joon Kim
2025	A	`conf`	DOTS: DRAM-PIM Optimization for Tall and Skinny GEMM Operations in LLM Inference. DATE Gyeonghwan Park, SangHyeok Han, Byungkuk Yoon, Jae-Joon Kim
2025	A	`conf`	Energy-Efficient Accelerator for Scalable Point Transformer Networks with Reduced Data Access. ICCAD Hyunsung Yoon, Jehun Lee, Jae-Joon Kim
2025	J	`jnl`	FastKV: KV Cache Compression for Fast Long-Context Processing with Token-Selective Propagation. CoRR Dongwon Jo, Jiwon Song, Yulhwa Kim, Jae-Joon Kim
2025	A	`conf`	Integer Unit-Based Outlier-Aware LLM Accelerator Preserving Numerical Accuracy of FP-FP GEMM. DATE Jehun Lee, Jae-Joon Kim
2025	—	`conf`	L4Q: Parameter Efficient Quantization-Aware Fine-Tuning on Large Language Models. ACL (1) Hyesung Jeon, Yulhwa Kim, Jae-Joon Kim
2025	A	`conf`	LLM-on-the-Palm: Mobile LLM Inference with PIM-Enhanced NAND Flash Memory. ICCAD HyunJin Kim, SangHyeok Han, Jae-Joon Kim
2025	J	`jnl`	LiteStage: Latency-aware Layer Skipping for Multi-stage Reasoning. CoRR Beomseok Kang, Jiwon Song, Jae-Joon Kim
2025	J	`jnl`	Multifunctional In-Memory Analog-to-Digital Converter for Next-Gen Compute-in-Memory Systems. Adv. Intell. Syst. Jiseong Im, JongHyun Ko, Joon Hwang, Jangsaeng Kim, Wonjun Shin, Ryun-Han Koo, MinKyu Park, Sung-Ho Park, Woo Young Choi, Jae-Joon Kim, Jong-Ho Lee
2025	A*	`conf`	Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding. DAC SangHyeok Han, Byungkuk Yoon, Gyeonghwan Park, Choungki Song, Dongkyun Kim, Jae-Joon Kim
2025	J	`jnl`	NeuroTorch: DRAM-free nonvolatile memory-based hybrid training compute-in-memory system simulator. Neurocomputing JongHyun Ko, Inseok Lee, Kyu-Ho Lee, Joon Hwang, Min-Kyu Park, Jiseong Im, Jeonghyun Kim, Ryun-Han Koo, Sung-Ho Park, Jae-Joon Kim, Jong-Ho Lee
2025	A	`conf`	Partial-Sum Quantization Based on Pseudo-Quantization Noise for Variation-Tolerant Analog In-Memory Computing. ISLPED Nameun Kang, Eunhyeok Park, Sangsu Park, Jongil Kim, Jaeyun Yi, Jae-Joon Kim
2025	J	`jnl`	QWHA: Quantization-Aware Walsh-Hadamard Adaptation for Parameter-Efficient Fine-Tuning on Large Language Models. CoRR Hyesung Jeon, Seojune Lee, Beomseok Kang, Yulhwa Kim, Jae-Joon Kim
2025	J	`jnl`	Reasoning Path Compression: Compressing Generation Trajectories for Efficient LLM Reasoning. CoRR Jiwon Song, Dongwon Jo, Yulhwa Kim, Jae-Joon Kim
2025	J	`jnl`	Retrospective Sparse Attention for Efficient Long-Context Generation. CoRR Seonghwan Choi, Beomseok Kang, Dongwon Jo, Jae-Joon Kim
2025	A*	`conf`	SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM. DAC Byungkuk Yoon, SangHyeok Han, Gyeonghwan Park, Jae-Joon Kim
2024	A*	`conf`	4-Transistor Ternary Content Addressable Memory Cell Design using Stacked Hybrid IGZO/Si Transistors. DAC Munhyeon Kim, Jae-Joon Kim
2024	—	`conf`	A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions. CICC Eunhwan Kim, Hyunmyung Oh, Jehun Lee, Jihoon Park, Myeongeun Kwon, Jae-Joon Kim
2024	A*	`conf`	FIGNA: Integer Unit-Based Accelerator Design for FP-INT GEMM Preserving Numerical Accuracy. HPCA Jaeyong Jang, Yulhwa Kim, Juheun Lee, Jae-Joon Kim
2024	A*	`conf`	Fused Sampling and Grouping with Search Space Reduction for Efficient Point Cloud Acceleration. DAC Hyunsung Yoon, Jae-Joon Kim
2024	J	`jnl`	L4Q: Parameter Efficient Quantization-Aware Training on Large Language Models via LoRA-wise LSQ. CoRR Hyesung Jeon, Yulhwa Kim, Jae-Joon Kim
2024	A*	`conf`	Mixture of Scales: Memory-Efficient Token-Adaptive Binarization for Large Language Models. NeurIPS Dongwon Jo, Taesu Kim, Yulhwa Kim, Jae-Joon Kim
2024	J	`jnl`	Mixture of Scales: Memory-Efficient Token-Adaptive Binarization for Large Language Models. CoRR Dongwon Jo, Taesu Kim, Yulhwa Kim, Jae-Joon Kim
2024	J	`jnl`	Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sungju Ryu, Jaeyong Jang, Youngtaek Oh, Jae-Joon Kim
2024	A*	`conf`	SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks. ICML Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim
2024	J	`jnl`	SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks. CoRR Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim
2024	J	`jnl`	SNNSim: Investigation and Optimization of Large-Scale Analog Spiking Neural Networks Based on Flash Memory Devices. Adv. Intell. Syst. JongHyun Ko, Dongseok Kwon, Joon Hwang, Kyu-Ho Lee, Seongbin Oh, Jeonghyun Kim, Jiseong Im, Ryun-Han Koo, Jae-Joon Kim, Jong-Ho Lee
2023	J	`jnl`	1/ Adv. Intell. Syst. Wonjun Shin, Kyung Kyu Min, Jong-Ho Bae, Jaehyeon Kim, Ryun-Han Koo, Dongseok Kwon, Jae-Joon Kim, Daewoong Kwon, Jong-Ho Lee
2023	J	`jnl`	A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range. IEEE Trans. Circuits Syst. II Express Briefs Eunhwan Kim, Hyunmyung Oh, Nameun Kang, Jihoon Park, Jae-Joon Kim
2023	J	`jnl`	Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Sungju Ryu, Youngtaek Oh, Jae-Joon Kim
2023	A	`conf`	Efficient Sampling and Grouping Acceleration for Point Cloud Deep Learning via Single Coordinate Comparison. ICCAD Hyunsung Yoon, Jae-Joon Kim
2023	A*	`conf`	INSTA-BNN: Binary Neural Network with INSTAnce-aware Threshold. ICCV Changhun Lee, Hyungjun Kim, Eunhyeok Park, Jae-Joon Kim
2023	A*	`conf`	In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time. DAC Inhwan Lee, Eunhwan Kim, Nameun Kang, Hyunmyung Oh, Jae-Joon Kim
2023	A*	`conf`	Leveraging Early-Stage Robustness in Diffusion Models for Efficient and High-Quality Image Synthesis. NeurIPS Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Taesu Kim, Daehyun Ahn, Hyungjun Kim, Jae-Joon Kim
2023	A	`conf`	Searching for Robust Binary Neural Networks via Bimodal Parameter Perturbation. WACV Daehyun Ahn, Hyungjun Kim, Taesu Kim, Eunhyeok Park, Jae-Joon Kim
2023	J	`jnl`	Squeezing Large-Scale Diffusion Models for Mobile. CoRR Jiwoong Choi, Minkyu Kim, Daehyun Ahn, Taesu Kim, Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Jae-Joon Kim, Hyungjun Kim
2023	J	`jnl`	V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taesu Kim, Daehyun Ahn, Dongsoo Lee, Jae-Joon Kim
2023	A*	`conf`	Winning Both the Accuracy of Floating Point Activation and the Simplicity of Integer Arithmetic. ICLR Yulhwa Kim, Jaeyong Jang, Jehun Lee, Jihoon Park, Jeonghoon Kim, Byeongwook Kim, Baeseong Park, Se Jung Kwon, Dongsoo Lee, Jae-Joon Kim
2022	J	`jnl`	AutoRelax: HW-SW Co-Optimization for Efficient SpGEMM Operations With Automated Relaxation in Deep Learning. IEEE Trans. Emerg. Top. Comput. Sehun Park, Jae-Joon Kim, Jaeha Kung
2022	J	`jnl`	BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks. IEEE J. Solid State Circuits Sungju Ryu, Hyungjun Kim, Wooseok Yi, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim
2022	J	`jnl`	Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators. ACM J. Emerg. Technol. Comput. Syst. Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim
2022	J	`jnl`	INSTA-BNN: Binary Neural Network with INSTAnce-aware Threshold. CoRR Changhun Lee, Hyungjun Kim, Eunhyeok Park, Jae-Joon Kim
2022	A*	`conf`	TAIM: ternary activation in-memory computing hardware with 6T SRAM array. DAC Nameun Kang, Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim
2022	A	`conf`	Workload-Balanced Graph Attention Network Accelerator with Top-K Aggregation Candidates. ICCAD Naebeom Park, Daehyun Ahn, Jae-Joon Kim
2021	—	`conf`	Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS. A-SSCC Hyunmyung Oh, Hyungjun Kim, Daehyun Ahn, Jihoon Park, Yulhwa Kim, Inhwan Lee, Jae-Joon Kim
2021	J	`jnl`	High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory. ACM Trans. Design Autom. Electr. Syst. Naebeom Park, Sungju Ryu, Jaeha Kung, Jae-Joon Kim
2021	A*	`conf`	Improving Accuracy of Binary Neural Networks Using Unbalanced Activation Distribution. CVPR Hyungjun Kim, Jihoon Park, Changhun Lee, Jae-Joon Kim
2021	A	`conf`	Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. DATE Yulhwa Kim, Hyungjun Kim, Jihoon Park, Hyunmyung Oh, Jae-Joon Kim
2021	J	`jnl`	Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators. IEEE Access Daehyun Ahn, Hyunmyung Oh, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim
2021	A	`conf`	Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow. ICCAD Sungju Ryu, Youngtaek Oh, Jae-Joon Kim
2021	A	`conf`	SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching. DATE Sungju Ryu, Youngtaek Oh, Taesu Kim, Daehyun Ahn, Jae-Joon Kim
2021	—	`conf`	Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks. AICAS Hyunmyung Oh, Hyungjun Kim, Nameun Kang, Yulhwa Kim, Jihoon Park, Jae-Joon Kim
2021	J	`jnl`	Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations. IEEE J. Solid State Circuits Sungju Ryu, Jongeun Koo, Wook Kim, Yonghwan Kim, Jae-Joon Kim
2020	—	`conf`	A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS. CICC Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim
2020	—	`conf`	A Novel In-DRAM Accelerator Architecture for Binary Neural Network. COOL CHIPS Haerang Choi, Yosep Lee, Jae-Joon Kim, Sungjoo Yoo
2020	A*	`conf`	Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead. DAC Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim
2020	J	`jnl`	Balancing Computation Loads and Optimizing Input Vector Loading in LSTM Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Junki Park, Wooseok Yi, Daehyun Ahn, Jaeha Kung, Jae-Joon Kim
2020	A*	`conf`	BinaryDuo: Reducing Gradient Mismatch in Binary Activation Network by Coupling Binary Activations. ICLR Hyungjun Kim, Kyungsu Kim, Jinseok Kim, Jae-Joon Kim
2020	J	`jnl`	BinaryDuo: Reducing Gradient Mismatch in Binary Activation Network by Coupling Binary Activations. CoRR Hyungjun Kim, Kyungsu Kim, Jinseok Kim, Jae-Joon Kim
2020	A	`conf`	Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization. ICCAD Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim
2020	J	`jnl`	GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Semisupervised Learning and Bayesian Inference. IEEE Trans. Neural Networks Learn. Syst. Wooseok Yi, Junki Park, Jae-Joon Kim
2020	J	`jnl`	Improving Accuracy of Binary Neural Networks using Unbalanced Activation Distribution. CoRR Hyungjun Kim, Jihoon Park, Changhun Lee, Jae-Joon Kim
2020	—	`conf`	OPTIMUS: OPTImized matrix MUltiplication Structure for Transformer neural network accelerator. MLSys Junki Park, Hyunsung Yoon, Daehyun Ahn, Jungwook Choi, Jae-Joon Kim
2020	A	`conf`	Time-step interleaved weight reuse for LSTM neural network computing. ISLPED Naebeom Park, Yulhwa Kim, Daehyun Ahn, Taesu Kim, Jae-Joon Kim
2020	A*	`conf`	Unifying Activation- and Timing-based Learning Rules for Spiking Neural Networks. NeurIPS Jinseok Kim, Kyungsu Kim, Jae-Joon Kim
2020	J	`jnl`	Unifying Activation- and Timing-based Learning Rules for Spiking Neural Networks. CoRR Jinseok Kim, Kyungsu Kim, Jae-Joon Kim
2020	A	`conf`	V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning. FPGA Taesu Kim, Daehyun Ahn, Jae-Joon Kim
2019	—	`conf`	Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors. CICC Jongeun Koo, Jinseok Kim, Sungju Ryu, Chulsoo Kim, Jae-Joon Kim
2019	—	`conf`	Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array. VLSI Circuits Jinseok Kim, Jongeun Koo, Taesu Kim, Yulhwa Kim, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim
2019	A*	`conf`	BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation. DAC Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jae-Joon Kim
2019	J	`jnl`	BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function. CoRR Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim
2019	—	`conf`	Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping. A-SSCC Jongeun Koo, Eunhwan Kim, Seunghyun Yoo, Taesu Kim, Sungju Ryu, Jae-Joon Kim
2019	—	`conf`	Double Viterbi: Weight Encoding for High Compression Ratio and Fast On-Chip Reconstruction for Deep Neural Network. ICLR (Poster) Daehyun Ahn, Dongsoo Lee, Taesu Kim, Jae-Joon Kim
2019	A	`conf`	Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array. DATE Wooseok Yi, Yulhwa Kim, Jae-Joon Kim
2019	J	`jnl`	Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator. IEEE Trans. Very Large Scale Integr. Syst. Sungju Ryu, Naebeom Park, Jae-Joon Kim
2019	—	`conf`	In-memory batch-normalization for resistive memory based binary neural network hardware. ASP-DAC Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim
2019	J	`jnl`	Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines. IEICE Electron. Express Jongeun Koo, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim
2019	J	`jnl`	Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. IEEE Micro Shihui Yin, Jae-sun Seo, Yulhwa Kim, Xu Han, Hugh J. Barnaby, Shimeng Yu, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae-Joon Kim
2019	A*	`conf`	Peregrine: A Flexible Hardware Accelerator for LSTM with Limited Synaptic Connection Patterns. DAC Jaeha Kung, Junki Park, Sehun Park, Jae-Joon Kim
2019	J	`jnl`	Zero-shifting Technique for Deep Neural Network Training on Resistive Cross-point Arrays. CoRR Hyungjun Kim, Malte J. Rasch, Tayfun Gokmen, Takashi Ando, Hiroyuki Miyazoe, Jae-Joon Kim, John Rozen, Seyoung Kim
2018	A	`conf`	Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. ISLPED Jinseok Kim, Yulhwa Kim, Sungho Kim, Jae-Joon Kim
2018	J	`jnl`	Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics. ACM J. Emerg. Technol. Comput. Syst. Hyungjun Kim, Taesu Kim, Jinseok Kim, Jae-Joon Kim
2018	A	`conf`	Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array. ISLPED Yulhwa Kim, Hyungjun Kim, Daehyun Ahn, Jae-Joon Kim
2018	A	`conf`	Maximizing system performance by balancing computation loads in LSTM accelerators. DATE Junki Park, Jaeha Kung, Wooseok Yi, Jae-Joon Kim
2018	J	`jnl`	Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators. CoRR Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim
2018	—	`conf`	Viterbi-based Pruning for Sparse Matrix with Fixed and High Index Compression Ratio. ICLR (Poster) Dongsoo Lee, Daehyun Ahn, Taesu Kim, Pierce I-Jen Chuang, Jae-Joon Kim
2017	—	`conf`	8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors. ISSCC Eunhwan Kim, Minah Lee, Jae-Joon Kim
2017	J	`jnl`	Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics. CoRR Hyungjun Kim, Taesu Kim, Jinseok Kim, Jae-Joon Kim
2017	C	`conf`	GeCo: classification restricted Boltzmann machine hardware for on-chip learning. RSP Wooseok Yi, Junki Park, Jae-Joon Kim
2017	A	`conf`	Low design overhead timing error correction scheme for elastic clock methodology. ISLPED Sungju Ryu, Jongeun Koo, Jae-Joon Kim
2016	—	`conf`	Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines. A-SSCC Jongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim
2016	J	`jnl`	One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. IEEE Trans. Very Large Scale Integr. Syst. Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
2016	—	`ed.`	VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers VLSI-SoC (Selected Papers) Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis
2015	J	`jnl`	Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Insup Shin, Jae-Joon Kim, Youngsoo Shin
2014	A	`conf`	Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs. DATE Hayoung Kim, Dongyoung Kim, Jae-Joon Kim, Sungjoo Yoo, Sunggu Lee
2014	—	`conf`	Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. ASP-DAC Insup Shin, Jae-Joon Kim, Youngsoo Shin
2013	A	`conf`	A pipeline architecture with 1-cycle timing error correction for low voltage operations. ISLPED Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin
2013	J	`jnl`	Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. IEEE Trans. Very Large Scale Integr. Syst. Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
2012	—	`conf`	Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design. ISVLSI Xiuyuan Bi, Hai Li, Jae-Joon Kim
2011	A	`conf`	Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. ISLPED Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy
2011	J	`jnl`	Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. IEEE Trans. Very Large Scale Integr. Syst. Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy
2011	J	`jnl`	SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
2010	J	`jnl`	Self-Repairing SRAM Using On-Chip Detection and Compensation. IEEE Trans. Very Large Scale Integr. Syst. Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy
2010	—	`conf`	Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. CICC Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim
2009	J	`jnl`	A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. IEEE J. Solid State Circuits Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy
2009	J	`jnl`	A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry. IEEE J. Solid State Circuits Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim
2009	J	`jnl`	Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectron. Reliab. Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang
2008	—	`conf`	A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS. ISSCC Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy
2008	—	`conf`	A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement. ISSCC Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim
2008	C	`conf`	Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
2008	Misc	`conf`	Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy
2008	Misc	`conf`	On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
2008	Misc	`conf`	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy
2007	J	`jnl`	Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectron. J. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
2006	J	`jnl`	A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. Jae-Joon Kim, Kaushik Roy
2006	J	`jnl`	PVT-aware leakage reduction for on-die caches with improved read stability. IEEE J. Solid State Circuits Chris Hyung-Il Kim, Jae-Joon Kim, Ik-Joon Chang, Kaushik Roy
2006	A	`conf`	Robust level converter design for sub-threshold logic. ISLPED Ik Joon Chang, Jae-Joon Kim, Kaushik Roy
2005	J	`jnl`	A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. Very Large Scale Integr. Syst. Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
2005	—	`conf`	Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
2003	A	`conf`	A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy