Jae-Jin Lee

63 papers A 6B 2C 4Journal 36Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
TT-SEAL: TTD-Aware Selective Encryption for Adversarially-Robust and Low-Latency Edge AI.
CoRR
Kyeongpil Min, Sangmin Jeon, Jae-Jin Lee, Woojoo Lee
2025 A conf
ASAP-FE: Energy-Efficient Feature Extraction Enabling Multi-Channel Keyword Spotting on Edge Processors.
ISLPED
Jongin Choi, Jina Park, Jae-Jin Lee, Massoud Pedram, Woojoo Lee
2025 J jnl
ASAP-FE: Energy-Efficient Feature Extraction Enabling Multi-Channel Keyword Spotting on Edge Processors.
CoRR
Jongin Choi, Jina Park, Woojoo Lee, Jae-Jin Lee, Massoud Pedram
2025 J jnl
BCRNet-SNN: Body Channel Response-Aware Spiking Neural Network for User Recognition.
IEEE Trans. Ind. Informatics
Taewook Kang, ChanWoo Shin, Jongseok Lee, Jae-Jin Lee, Donggyu Sim, Seong-Eun Kim
2025 J jnl
Electromagnetic Interference-Robust Fingerprint Spoof Detection Based on Finger Channel Response.
IEEE Trans. Ind. Informatics
Taewook Kang, Kwang-Il Oh, Seong-Eun Kim, Jae-Jin Lee, Sungeun Kim, Kyungjin Byun, Woojoo Lee, Wangrok Oh
2025 J jnl
FiCABU: A Fisher-Based, Context-Adaptive Machine Unlearning Processor for Edge AI.
CoRR
Eun-Su Cho, Jongin Choi, Jeongmin Jin, Jae-Jin Lee, Woojoo Lee
2025 J jnl
LoRA-Edge: Tensor-Train-Assisted LoRA for Practical CNN Fine-Tuning on Edge Devices.
CoRR
Hyunseok Kwak, Kyeongwon Lee, Jae-Jin Lee, Woojoo Lee
2025 B conf
NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA Prototyping.
FPL
Kyuseung Han, Hyeonguk Jang, Sukho Lee, Sung-Eun Kim, Kyudong Hwang, Jae-Jin Lee
2025 B conf
NeuGEMM: A Reordering-Free Unified GEMM-Conv2D Accelerator for Lightweight Neuromorphic Processors.
FPL
Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han
2025 J jnl
Standalone FPGA-Based QAOA Emulator for Weighted-MaxCut on Embedded Devices.
CoRR
Seonghyun Choi, Kyeongwon Lee, Jae-Jin Lee, Woojoo Lee
2024 J jnl
Anti-Spoofing for Fingerprint Recognition Using Electric Body Pulse Response.
IEEE Internet Things J.
Taewook Kang, Kwang-Il Oh, Jae-Jin Lee, Sungeun Kim, Woojoo Lee, Wangrok Oh, Seong-Eun Kim
2024 J jnl
Day-Night architecture: Development of an ultra-low power RISC-V processor for wearable anomaly detection.
J. Syst. Archit.
Eunjin Choi, Jina Park, Kyeongwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee
2024 J jnl
Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jina Park, Kyuseung Han, Eunjin Choi, Jae-Jin Lee, Kyeongwon Lee, Woojoo Lee, Massoud Pedram
2024 — conf
Optimizing Implementation of SNN for Embedded System.
ICACT
Hyeonguk Jang, Jae-Jin Lee, Kyuseung Han
2024 A conf
STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs.
ISLPED
Kyuseung Han, Hyunseok Kwak, Kwang-Il Oh, Sukho Lee, Hyeonguk Jang, Jae-Jin Lee, Woojoo Lee
2023 A conf
Developing an Ultra-low Power RISC-V Processor for Anomaly Detection.
DATE
Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee
2023 A conf
Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU.
ISLPED
Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram
2022 — conf
A Logarithmic Domain Algorithm of the Hodgkin-Huxley Neuron Model for Hardware Implementations.
ICEIC
In-San Jeon, Hyuk Kim, Jae-Jin Lee
2022 — conf
Comparison between STDP and Gradient-descent Training Processes for Spiking Neural Networks Using MNIST Digits.
ICTC
Taewook Kang, Kwang-Il Oh, Jae-Jin Lee, Wangrok Oh
2022 — conf
Releasing the Memory Bottleneck to Display Video Correctly.
ISOCC
Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han
2022 J jnl
Spiking Neural Networks-Inspired Signal Detection Based on Measured Body Channel Response.
IEEE Trans. Instrum. Meas.
Taewook Kang, Kwang-Il Oh, Jae-Jin Lee, Sungeun Kim, Seoung-Eun Kim, Woojoo Lee, Wangrok Oh
2021 J jnl
Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes.
IEEE Internet Things J.
Kyuseung Han, Sukho Lee, Kwang-Il Oh, Younghwan Bae, Hyeonguk Jang, Jae-Jin Lee, Woojoo Lee, Massoud Pedram
2021 J jnl
Developing a Multicore Platform Utilizing Open RISC-V Cores.
IEEE Access
Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Seung-Yeong Lee, Jae-Hyoung Lee, Woojoo Lee
2021 J jnl
Energy efficient spiking neural network processing using approximate arithmetic units and variable precision weights.
J. Parallel Distributed Comput.
Yi Wang, Hao Zhang, Kwang-Il Oh, Jae-Jin Lee, Seok-Bum Ko
2021 J jnl
Measurement and Analysis of Human Body Channel Response for Biometric Recognition.
IEEE Trans. Instrum. Meas.
Taewook Kang, Kwang-Il Oh, Jae-Jin Lee, Beom-Su Park, Wangrok Oh, Seong-Eun Kim
2021 J jnl
Measurement and Evaluation of Electric Signal Transmission Through Human Body by Channel Modeling, System Design, and Implementation.
IEEE Trans. Instrum. Meas.
Taewook Kang, Jung-Hwan Hwang, Hyuk Kim, Sungeun Kim, Kwang-Il Oh, Jae-Jin Lee, Hyung-Il Park, Seong-Eun Kim, Wangrok Oh, Woojoo Lee
2020 J jnl
A Switched Capacitor Voltage Converter With Exponentially Sized Capacitor Banks for Wide Load Range.
IEEE Trans. Circuits Syst. II Express Briefs
Syed Asmat Ali Shah, Saad Arslan, Jae-Jin Lee, Bo-Seok Seo, HyungWon Kim
2020 J jnl
Evaluation of Human Body Characteristics for Electric Signal Transmission Based on Measured Body Impulse Response.
IEEE Trans. Instrum. Meas.
Taewook Kang, Sungeun Kim, Kwang-Il Oh, Jung-Hwan Hwang, Jae-Jin Lee, Hyungil Park, Kyungjin Byun, Woojoo Lee
2020 J jnl
User Recognition Based on Human Body Impulse Response: A Feasibility Study.
IEEE Access
Jin-Ho Chung, Taewook Kang, Dohyun Kwun, Jae-Jin Lee, Seong-Eun Kim
2019 J jnl
A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties.
IEEE Des. Test
Kyuseung Han, Jae-Jin Lee, Woojoo Lee, Jinho Lee
2019 J jnl
Efficient spiking neural network training and inference with reduced precision memory and computing.
IET Comput. Digit. Tech.
Yi Wang, Karim Shahbazi, Hao Zhang, Kwang-Il Oh, Jae-Jin Lee, Seok-Bum Ko
2019 J jnl
MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems.
IEEE Access
Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee
2019 — conf
Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications.
ISOCC
Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee
2019 J jnl
TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Woojoo Lee, Taewook Kang, Jae-Jin Lee, Kyuseung Han, Joongheon Kim, Massoud Pedram
2019 A conf
TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform.
ISLPED
Kyuseung Han, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram
2018 J jnl
84% High efficiency dynamic voltage scaler with nano-second settling time based on charge-pump and BWC-DAC.
Microelectron. J.
A. N. Ragheb, HyungWon Kim, Jae-Jin Lee
2018 J jnl
An Energy Efficient Charging Technique for Switched Capacitor Voltage Converters With Low-Duty Ratio.
IEEE Trans. Circuits Syst. II Express Briefs
Saad Arslan, Syed Asmat Ali Shah, Jae-Jin Lee, HyungWon Kim
2018 J jnl
TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kyuseung Han, Jae-Jin Lee, Jinho Lee, Woojoo Lee, Massoud Pedram
2017 J jnl
Energy-Efficient Stabilized Automatic Control for Multicore Baseband in Millimeter-Wave Systems.
IEEE Access
Joongheon Kim, Jae-Jin Lee, Jong-Kook Kim, Woojoo Lee
2017 J jnl
Strategic Control of 60 GHz Millimeter-Wave High-Speed Wireless Links for Distributed Virtual Reality Platforms.
Mob. Inf. Syst.
Joongheon Kim, Jae-Jin Lee, Woojoo Lee
2015 J jnl
Flexible Multi-Core Platform for a Multiple-Format Video Decoder.
J. Signal Process. Syst.
Hyun-Ho Jo, Yong-Jo Ahn, Dae-Beom Kang, Bongil Ji, Dong-Gyu Sim, Jae-Jin Lee
2015 C conf
Virtual prototype based on Aldebarn CPU core.
VLSI-SoC
Jae-Jin Lee, Chan Kim, Kyungjin Byun, Nak-Woong Eum
2013 J jnl
Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface.
IEEE Trans. Very Large Scale Integr. Syst.
Jang-Woo Lee, Hong-Jung Kim, Chun-Seok Jeong, Jae-Jin Lee, Changsik Yoo
2012 C conf
Cost-effective TSV redundancy configuration.
VLSI-SoC
Jongpil Jung, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, Chong-Min Kyung
2012 — conf
Multi-core architecture for video decoding.
ISOCC
Jae-Jin Lee, Kyungjin Byun, Nak-Woong Eum
2011 — conf
Application specific processor for multi-standard video decoding.
ISOCC
Jae-Jin Lee, Nak-Woong Eum
2011 — conf
Design and verification of an application-specific PLD using VHDL and SystemVerilog.
ASICON
Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song
2010 J jnl
Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism.
IET Circuits Devices Syst.
Jun-Young Lee, Jae-Jin Lee, Seongmo Park
2010 J jnl
New Lookup Tables and Searching Algorithms for Fast H.264/AVC CAVLC Decoding.
IEEE Trans. Circuits Syst. Video Technol.
Jun-Young Lee, Jae-Jin Lee, Seongmo Park
2009 J jnl
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control.
IEEE J. Solid State Circuits
Hae-Kang Jung, Kyoungho Lee, Jong-Sam Kim, Jae-Jin Lee, Jae-Yoon Sim, Hong-June Park
2009 J jnl
A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Suk Seo, Jang-Woo Lee, Hong-Jung Kim, Changsik Yoo, Jae-Jin Lee, Chun-Seok Jeong
2008 C conf
A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder.
ISCAS
Jun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park
2008 C conf
Service Impact Analysis Framework Using Service Model for Integrated Service Resource Management of NGN Services.
APNOMS
Seung Hee Han, Bom Soo Kim, Chan Kyou Hwang, Jae-Jin Lee
2007 — conf
Design of a Reversible PLD Architecture.
ARC
Jae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song
2006 — conf
High-Level Synthesis Using SPARK and Systolic Array.
ARC
Jae-Jin Lee, Gi-Yong Song
2006 — conf
Super Semi-systolic Array-Based Application-Specific PLD Architecture.
ARC
Jae-Jin Lee, Gi-Yong Song
2005 J jnl
A New Application-Specific PLD Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jae-Jin Lee, Gi-Yong Song
2005 — conf
Design of an application-specific PLD architecture.
ASP-DAC
Jae-Jin Lee, Gi-Yong Song
2004 A conf
Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier.
FPGA
Jae-Jin Lee, Gi-Yong Song
2004 — conf
Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM.
ESSCIRC
Chun-Seok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih
2004 — conf
The VDSL Deployments and Their Associated Crosstalk with xDSL Systems.
ICT
Kyung-Ah Han, Jae-Jin Lee, Jae-Cheol Ryou
2003 — conf
Implementation of the super-systolic array for convolution.
ASP-DAC
Jae-Jin Lee, Gi-Yong Song
1997 J jnl
A 200 MHz register-based wave-pipelined 64 M synchronous DRAM.
IEEE J. Solid State Circuits
Ho-Jun Song, Jung-Pill Kim, Jae-Jin Lee, Jong-Hoon Oh, Seung-Han Ahn, Inseok Hwang