Jacques Benkoski

15 papers A* 2A 3Journal 3Unranked 7

Year	Rank	Type	Title / Venue / Authors
2007	—	`conf`	Do Digital Design and Variability Mix like Oil and Water? ISQED Jacques Benkoski, Michelle Clancy, Shankar Krishnamoorthy, David Holt, Ravi Subramanian, Clive Bittlestone, Tsuyoshi Yamamoto, Andrew Kanhg
2002	A	`conf`	Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. DATE K. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment
2001	—	`conf`	0.13 micron: Will the Speed Bumps Slow the Race to Market? ISQED Bill Alexander, Jacques Benkoski
2000	—	`conf`	How Do You Select A High Quality EDA Tool Flow?. ISQED Robert N. Blair, Jacques Benkoski
1993	—	`conf`	Demosthenes-A technology-independent power DMOS layout generator. EURO-DAC Gilles Fourneris, Nourouddine Bekkara, Jacques Benkoski, Lucia Zullino, Dino Spatafora, Giuseppe Martino
1993	J	`jnl`	Yield optimization of analog ICs using two-step analytic modeling methods. IEEE J. Solid State Circuits Carlo Guardiani, Primo Scandolara, Jacques Benkoski, Germano Nicollini
1992	—	`conf`	Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulation. EURO-DAC Ronald B. Stewart, Véronique Anjubault, Philippe Garcin, Jacques Benkoski
1991	—	`conf`	Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator. EURO-DAC Joel Besnard, Jacques Benkoski, Bernard Hennion
1991	A	`conf`	Static Timing Analysis Using Interval Constraints. ICCAD Ronald B. Stewart, Jacques Benkoski
1991	—	`conf`	TATOO: an industrial timing analyzer with false path elimination and test pattern generation. EURO-DAC Jacques Benkoski, Ronald B. Stewart
1991	A*	`conf`	The Role of Timing Verification in Layout Synthesis. DAC Jacques Benkoski, Andrzej J. Strojwas
1990	J	`jnl`	Timing verification using statically sensitizable paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man
1989	A	`conf`	Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. ITC Jacques Benkoski, Andrzej J. Strojwas
1989	A*	`conf`	Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. DAC Jacques Benkoski, Andrzej J. Strojwas
1987	J	`jnl`	A New Approach to Hierarchical and Statistical Timing Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jacques Benkoski, Andrzej J. Strojwas