Jacob Savir

88 papers A* 1A 17C 3Misc 8Journal 48Unranked 11
YearRankTypeTitle / Venue / Authors
2006 Misc conf
BIST Pretest of ICs: Risks and Benefits.
VTS
Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
2006 J jnl
Coefficient-based test of parametric faults in analog circuits.
IEEE Trans. Instrum. Meas.
Zhen Guo, Jacob Savir
2006 J jnl
Effect of BIST Pretest on IC Defect Level.
IEICE Trans. Inf. Syst.
Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
2005 J jnl
Built-in online and offline test of airborne digital systems.
IEEE Trans. Instrum. Meas.
Jacob Savir
2005 J jnl
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST.
IEICE Trans. Inf. Syst.
Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
2005 J jnl
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.
IEICE Trans. Inf. Syst.
Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
2004 J jnl
Analog Circuit Test Using Transfer Function Coefficient Estimates.
IEICE Trans. Inf. Syst.
Zhen Guo, Jacob Savir
2004 — conf
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.
Asian Test Symposium
Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
2004 J jnl
Scan Latch Design for Test Applications.
J. Electron. Test.
Amit M. Sheth, Jacob Savir
2003 A conf
Analog Circuit Test using Transfer Function Coe .cient Estimates.
ITC
Zhen Guo, Jacob Savir
2003 J jnl
Single-clock, single-latch, scan design.
IEEE Trans. Instrum. Meas.
Amit M. Sheth, Jacob Savir
2003 J jnl
Test limitations of parametric faults in analog circuits.
IEEE Trans. Instrum. Meas.
Jacob Savir, Zhen Guo
2002 — conf
Observer-Based Test of Analog Linear Time-Invariant Circuits.
DELTA
Zhen Guo, Jacob Savir
2002 C conf
On the Detectability of Parametric Faults in Analog Circuits.
ICCD
Jacob Savir, Zhen Guo
2002 — conf
Test Limitations of Parametric Faults in Analog Circuits.
Asian Test Symposium
Jacob Savir, Zhen Guo
2001 J jnl
BIST Analysis of an Embedded Memory Associated Logic.
VLSI Design
Jacob Savir
2001 J jnl
BIST-Based Fault Diagnosis in the Presence of Embedded Memories.
VLSI Design
Jacob Savir
2001 — conf
On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks.
Asian Test Symposium
Zhen Guo, Xi Min Zhang, Jacob Savir, Yun-Qing Shi
2001 J jnl
Test Generators Need to be Modified to Handle CMOS Designs.
VLSI Design
Jacob Savir
2000 J jnl
Distributed BIST Architecture to Combat Delay Faults.
J. Electron. Test.
Jacob Savir
2000 A conf
MUST: multiple-stem analysis for identifying sequentially untestable faults.
ITC
Qiang Peng, Miron Abramovici, Jacob Savir
2000 — conf
On testing safety-sensitive digital systems.
Asian Test Symposium
Jacob Savir
2000 A conf
On-line and off-line test of airborne digital systems: a reliability study.
ITC
Jacob Savir
1999 C conf
Design for Testability to Combat Delay Faults.
ICCD
Jacob Savir
1999 J jnl
Distributed Generation of Weighted Random Patterns.
IEEE Trans. Computers
Jacob Savir
1999 — conf
Memory Chip BIST Architecture.
Great Lakes Symposium on VLSI
Jacob Savir
1999 J jnl
Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections.
J. Electron. Test.
Jacob Savir
1998 — conf
BIST Diagnostics, Part 1: Simulation Models.
Asian Test Symposium
Jacob Savir
1998 Misc conf
Distributed Generation of Weighted Random Patterns.
VTS
Jacob Savir
1998 J jnl
On-Chip Weighted Random Patterns.
J. Electron. Test.
Jacob Savir
1998 J jnl
Random Pattern Testability of Memory Control Logic.
IEEE Trans. Computers
Jacob Savir
1998 J jnl
Random pattern testability of memory address logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jacob Savir
1998 J jnl
Redundancy revisited.
IEEE Trans. Very Large Scale Integr. Syst.
Jacob Savir
1998 J jnl
Salvaging Test Windows in BIST Diagnostics.
IEEE Trans. Computers
Jacob Savir
1997 C conf
BIST-Based Fault Diagnosis in the Presence of Embedded Memories.
ICCD
Jacob Savir
1997 J jnl
Delay Test Generation: A Hardware Perspective.
J. Electron. Test.
Jacob Savir
1997 J jnl
Module Level Weighted Random Patterns.
J. Electron. Test.
Jacob Savir
1997 — conf
On Chip Weighted Random Patterns.
Asian Test Symposium
Jacob Savir
1997 — conf
On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers.
Asian Test Symposium
Jacob Savir
1997 Misc conf
Random pattern testability of memory control logic.
VTS
Jacob Savir
1997 J jnl
Reduced Latch Count Shift Registers.
J. Electron. Test.
Jacob Savir
1997 Misc conf
Salvaging test windows in BIST diagnostic.
VTS
Jacob Savir
1997 A conf
Scan Latch Design for Delay Test.
ITC
Jacob Savir
1996 Misc conf
Delay Fault Testing: How Robust are Our Models?
VTS
Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma
1996 J jnl
Reducing the MISR Size.
IEEE Trans. Computers
Jacob Savir
1995 — conf
Generator choices for delay test.
Asian Test Symposium
Jacob Savir
1995 — conf
Module level weighted random patterns.
Asian Test Symposium
Jacob Savir
1995 Misc conf
On shrinking wide compressors.
VTS
Jacob Savir
1995 J jnl
Shrinking wide compressors [BIST].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jacob Savir
1994 J jnl
Broad-side delay test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jacob Savir, Srinivas Patil
1994 Misc conf
On broad-side delay test.
VTS
Jacob Savir, Srinivas Patil
1994 J jnl
On broad-side delay test.
IEEE Trans. Very Large Scale Integr. Syst.
Jacob Savir, Srinivas Patil
1993 J jnl
Built-In Self-Test: Milestones and Challenges.
VLSI Design
Jacob Savir, Paul H. Bardell
1993 J jnl
Scan-based transition test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jacob Savir, Srinivas Patil
1992 J jnl
A Multiple Seed Linear Feedback Shift Register.
IEEE Trans. Computers
Jacob Savir, William H. McAnney
1992 J jnl
AC strength of a pattern generator.
J. Electron. Test.
Jacob Savir, Robert F. Berry
1992 Misc conf
Developments in delay testing.
VTS
Jacob Savir
1992 A conf
Skewed-Load Transition Test: Part 1, Calculus.
ITC
Jacob Savir
1992 A conf
Skewed-Load Transition Test: Part 2, Coverage.
ITC
Srinivas Patil, Jacob Savir
1992 J jnl
Statistical Resistance to Detection.
IEEE Trans. Computers
A. Boneh, Jacob Savir
1991 A conf
At-Speed Test is not Necessarily an AC Test.
ITC
Jacob Savir, Robert F. Berry
1991 J jnl
Partitioning of polynomial tasks: test generation, an example.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jacob Savir, Paul H. Bardell
1991 J jnl
Testing for Coupled Cells in Random-Access Memories.
IEEE Trans. Computers
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
1990 A conf
A multiple seed linear feedback shift register.
ITC
Jacob Savir, William H. McAnney
1990 A conf
AC product defect level and yield loss.
ITC
Jacob Savir
1989 A conf
Testing for Coupled Cells in Random-Access Memories.
ITC
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
1988 J jnl
Built-In Checking of the Correct Self-Test Signature.
IEEE Trans. Computers
William H. McAnney, Jacob Savir
1988 A conf
Identification of Failing Tests with Cycling Registers.
ITC
Jacob Savir, William H. McAnney
1988 J jnl
Random Pattern Testability of Delay Faults.
IEEE Trans. Computers
Jacob Savir, William H. McAnney
1988 A* conf
Why Partial Design Verification Works Better Than It Should.
DAC
Jacob Savir
1987 J jnl
Fault Propagation Through Embedded Multiport Memories.
IEEE Trans. Computers
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
1986 A conf
Built-In Checking of the Correct Self-Test Signature.
ITC
William H. McAnney, Jacob Savir
1986 A conf
Random Pattern Testability of Delay Faults.
ITC
Jacob Savir, William H. McAnney
1986 J jnl
The Bidirectional Double Latch (BDDL).
IEEE Trans. Computers
Jacob Savir
1985 J jnl
Layout Influences Testability.
IEEE Trans. Computers
Thomas H. Spencer, Jacob Savir
1985 A conf
Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory.
ITC
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
1985 A conf
Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory.
ITC
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
1984 J jnl
On Random Pattern Test Length.
IEEE Trans. Computers
Jacob Savir, Paul H. Bardell
1984 J jnl
Random Pattern Testability.
IEEE Trans. Computers
Jacob Savir, Gary S. Ditlow, Paul H. Bardell
1983 J jnl
A New Empirical Test for the Quality of Random Integer Generators.
IEEE Trans. Computers
Jacob Savir
1983 J jnl
Good Controllability and Observability Do Not Guarantee Good Testability.
IEEE Trans. Computers
Jacob Savir
1983 A conf
On Random Pattern Test Length.
ITC
Jacob Savir, Paul H. Bardell
1981 J jnl
Syndrome-Testing of "Syndrome-Untestable" Combinational Circuits.
IEEE Trans. Computers
Jacob Savir
1981 J jnl
The Weighted Syndrome Sums Approach to VLSI Testing.
IEEE Trans. Computers
Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith
1981 A conf
VLSI Self-Testing Based on Syndrome Techniques.
ITC
Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith
1980 J jnl
Detection of Single Intermittent Faults in Sequential Circuits.
IEEE Trans. Computers
Jacob Savir
1980 J jnl
Syndrome-Testable Design of Combinational Circuits.
IEEE Trans. Computers
Jacob Savir
1980 J jnl
Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection.
IEEE Trans. Computers
Jacob Savir