Jacob A. Abraham

449 papers A* 27A 76B 16C 37Misc 69Journal 121Unranked 103
YearRankTypeTitle / Venue / Authors
2025 J jnl
Built-off self-calibration scheme for ADCs based on shifting transfer-characteristics.
IEICE Electron. Express
Myeonggu Gil, Jaehyun Park, Jacob A. Abraham, Byoungho Kim
2025 J jnl
CLEAR Cross-Layer Resilience: A Retrospective.
IEEE Des. Test
Eric Cheng, Hyungmin Cho, Shahrzad Mirkhani, Lukasz G. Szafaryn, Jacob A. Abraham, Pradip Bose, Chen-Yong Cher, Klas Lilja, Kevin Skadron, Mircea Stan, Subhasish Mitra
2023 — conf
Secure Control Loop Execution of Cyber-Physical Devices Using Predictive State Space Checks.
ISQED
Kwondo Ma, Chandramouli N. Amarnath, Abhijit Chatterjee, Jacob A. Abraham
2022 J jnl
Selection scheme sensitivity for a hybrid Salp Swarm Algorithm: analysis and applications.
Eng. Comput.
Laith Mohammad Abualigah, Mohammad Shehab, Ali Diabat, Jacob A. Abraham
2021 J jnl
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor.
IEEE J. Solid State Circuits
Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
2021 J jnl
A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor.
IEEE J. Solid State Circuits
Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
2021 J jnl
Real-Time Error Detection in Nonlinear Control Systems Using Machine Learning Assisted State-Space Encoding.
IEEE Trans. Dependable Secur. Comput.
Suvadeep Banerjee, Balavinayagam Samynathan, Jacob A. Abraham, Abhijit Chatterjee
2021 J jnl
Training Multi-Bit Quantized and Binarized Networks with a Learnable Symmetric Quantizer.
IEEE Access
Phuoc Pham, Jacob A. Abraham, Jaeyong Chung
2021 J jnl
Training Multi-bit Quantized and Binarized Networks with A Learnable Symmetric Quantizer.
CoRR
Phuoc Pham, Jacob A. Abraham, Jaeyong Chung
2020 — conf
A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor.
VLSI Circuits
Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
2020 J jnl
Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters.
IEEE Access
Byoungho Kim, Jacob A. Abraham
2020 A conf
Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor.
ITC
Vijay Kiran Kalyanam, Eric Mahurin, Michael Spence, Jacob A. Abraham
2020 — conf
Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP.
CICC
Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham
2019 J jnl
A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers.
IEEE J. Solid State Circuits
Jie Fang, Chaoming Zhang, Frank Singor, Jacob A. Abraham
2019 A* conf
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead.
DAC
Eric Cheng, Daniel Mueller-Gritschneder, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Deming Chen, Hyungmin Cho, Yanjing Li, Uzair Sharif, Kevin Skadron, Mircea Stan, Ulf Schlichtmann, Subhasish Mitra
2019 C conf
Resiliency Demands on Next Generation Critical Embedded Systems.
IOLTS
Jacob A. Abraham
2019 J jnl
Spectral Leakage-Driven Loopback Scheme for Prediction of Mixed-Signal Circuit Specifications.
IEEE Trans. Ind. Electron.
Byoungho Kim, Jacob A. Abraham
2018 C conf
Cross-Layer Control Adaptation for Autonomous System Resilience.
IOLTS
Md Imran Momtaz, Suvadeep Banerjee, Sujay Pandey, Jacob A. Abraham, Abhijit Chatterjee
2018 C conf
ESIFT: Efficient System for Error Injection.
IOLTS
Ninghan Tian, Daniel G. Saab, Jacob A. Abraham
2018 C conf
Effective Control Flow Integrity Checks for Intrusion Detection.
IOLTS
Ameya Chaudhari, Jacob A. Abraham
2018 J jnl
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra
2017 J jnl
A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jie Fang, Shankar Thirunakkarasu, Xuefeng Yu, Fabian Silva-Rivas, Chaoming Zhang, Frank Singor, Jacob A. Abraham
2017 — conf
Automatic Assertion Generation for Simulation, Formal Verification and Emulation.
ISVLSI
Tong Zhang, Daniel G. Saab, Jacob A. Abraham
2017 C conf
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.
ICCD
Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra
2017 C conf
Design of efficient error resilience in signal processing and control systems: From algorithms to circuits.
IOLTS
Jacob A. Abraham, Suvadeep Banerjee, Abhijit Chatterjee
2017 — conf
Power prediction of embedded scalar and vector processor: Challenges and solutions.
ISQED
Vijay Kiran Kalyanam, Peter G. Sassone, Jacob A. Abraham
2017 J jnl
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience).
CoRR
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra
2016 J jnl
A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Immanuel Raja, Gaurab Banerjee, Mohamad A. Zeidan, Jacob A. Abraham
2016 J jnl
CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores.
CoRR
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra
2016 — conf
Checksum based error detection in linearized representations of non linear control systems.
LATS
Suvadeep Banerjee, Abhijit Chatterjee, Jacob A. Abraham
2016 A* conf
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores.
DAC
Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra
2016 — conf
Cross-layer resilience: are high-level techniques always better?
HLDVT
Jacob A. Abraham
2016 Misc conf
Design of Self Calibrating and Error Resilient Mixed-Signal Systems for Signal Processing, Communications and Control.
VLSID
Jacob A. Abraham, Abhijit Chatterjee
2016 A conf
Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states.
ITC
Suvadeep Banerjee, Abhijit Chatterjee, Jacob A. Abraham
2016 Misc conf
Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below.
VTS
Andrzej J. Strojwas, Jacob A. Abraham, Hong Hao, Max M. Shulaker
2016 — conf
Quality Aware Error Detection in 2-D Separable Linear Transformation.
ATS
Shih-Hsin Hu, Jacob A. Abraham
2016 — conf
Single Trojan injection model generation and detection.
LATS
Harini Bhamidipati, Daniel G. Saab, Jacob A. Abraham
2015 J jnl
Delay Defect Diagnosis Methodology Using Path Delay Measurements.
IEICE Trans. Electron.
Eun Jung Jang, Jaeyong Chung, Jacob A. Abraham
2015 J jnl
Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction.
J. Electron. Test.
Hsun-Cheng Lee, Jacob A. Abraham
2015 A conf
Efficient soft error vulnerability estimation of complex designs.
DATE
Shahrzad Mirkhani, Subhasish Mitra, Chen-Yong Cher, Jacob A. Abraham
2015 A conf
Formal Verification ATPG Search Engine Emulator (Abstract Only).
FPGA
Gregory Ford, Aswin Krishna, Jacob A. Abraham, Daniel G. Saab
2015 Misc conf
In-depth soft error vulnerability analysis using synthetic benchmarks.
VTS
Shahrzad Mirkhani, Balavinayagam Samynathan, Jacob A. Abraham
2015 C conf
Power-aware multi-voltage custom memory models for enhancing RTL and low power verification.
ICCD
Vijay Kiran Kalyanam, Martin Saint-Laurent, Jacob A. Abraham
2015 C conf
The future of fault tolerant computing.
IOLTS
Jacob A. Abraham, Ravishankar K. Iyer, Dimitris Gizopoulos, Dan Alexandrescu, Yervant Zorian
2015 Misc conf
Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control.
VLSID
Jacob A. Abraham, Abhijit Chatterjee
2014 C conf
A novel algorithm for sparse FFT pruning and its applications to OFDMA technology.
IPCCC
Shakeel S. Abdulla, Haewoon Nam, Jacob A. Abraham
2014 A conf
A novel low power 11-bit hybrid ADC using flash and delay line architectures.
DATE
Hsun-Cheng Lee, Jacob A. Abraham
2014 J jnl
Addressing failures in exascale computing.
Int. J. High Perform. Comput. Appl.
Marc Snir, Robert W. Wisniewski, Jacob A. Abraham, Sarita V. Adve, Saurabh Bagchi, Pavan Balaji, James F. Belak, Pradip Bose, Franck Cappello, Bill Carlson, Andrew A. Chien, Paul Coteus, Nathan DeBardeleben, Pedro C. Diniz, Christian Engelmann, Mattan Erez, Saverio Fazzari, Al Geist, Rinku Gupta, Fred Johnson, Sriram Krishnamoorthy, Sven Leyffer, Dean Liberty, Subhasish Mitra, Todd S. Munson, Rob Schreiber, Jon Stearley, Eric Van Hensbergen
2014 J jnl
Bitstream-Driven Built-In Characterization for Analog and Mixed-Signal Embedded Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Byoungho Kim, Jacob A. Abraham
2014 A conf
Connecting different worlds - Technology abstraction for reliability-aware design and Test.
DATE
Ulf Schlichtmann, Veit Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaß, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn
2014 J jnl
Dynamic Performance Characterization of Embedded Single-Ended Mixed-Signal Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Byoungho Kim, Jacob A. Abraham
2014 A conf
EAGLE: A regression model for fault coverage estimation using a simulation based metric.
ITC
Shahrzad Mirkhani, Jacob A. Abraham
2014 — conf
Error Resilient Real-Time State Variable Systems for Signal Processing and Control.
ATS
Suvadeep Banerjee, Álvaro Gómez-Pau, Abhijit Chatterjee, Jacob A. Abraham
2014 Misc conf
Fast evaluation of test vector sets using a simulation-based statistical metric.
VTS
Shahrzad Mirkhani, Jacob A. Abraham
2014 — conf
Harmonic distortion correction for 8-bit delay line ADC using gray code.
LATW
Hsun-Cheng Lee, Jacob A. Abraham
2014 — conf
Rethinking error injection for effective resilience.
ASP-DAC
Shahrzad Mirkhani, Hyungmin Cho, Subhasish Mitra, Jacob A. Abraham
2014 Misc conf
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players?
VTS
Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda
2013 J jnl
A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories.
IEEE Trans. Very Large Scale Integr. Syst.
Jaeyong Chung, Joonsung Park, Jacob A. Abraham
2013 Misc conf
A framework for low overhead hardware based runtime control flow error detection and recovery.
VTS
Ameya Chaudhari, Junyoung Park, Jacob A. Abraham
2013 A conf
Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults.
ITC
Mahesh Prabhu, Jacob A. Abraham
2013 J jnl
Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohamad A. Zeidan, Gaurab Banerjee, Jacob A. Abraham
2013 J jnl
Capacitor-Coupled Built-Off Self-Test in Analog and Mixed-Signal Embedded Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Byoungho Kim, Jacob A. Abraham
2013 J jnl
Concurrent Path Selection Algorithm in Statistical Timing Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Jaeyong Chung, Jacob A. Abraham
2013 — conf
Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion Correction.
Asian Test Symposium
Hsun-Cheng Lee, Jacob A. Abraham
2013 Misc conf
Dynamic Trace Signal Selection for Post-Silicon Validation.
VLSI Design
Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham
2013 Misc conf
Enhanced algorithm of combining trace and scan signals in post-silicon validation.
VTS
Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham
2013 A conf
Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor.
DATE
Junyoung Park, Ameya Chaudhari, Jacob A. Abraham
2013 — conf
On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs.
ISQED
Vinod Viswanath, Rajeev Muralidhar, Harinarayanan Seshadri, Jacob A. Abraham
2013 A* conf
Quantitative evaluation of soft error injection techniques for robust system design.
DAC
Hyungmin Cho, Shahrzad Mirkhani, Chen-Yong Cher, Jacob A. Abraham, Subhasish Mitra
2013 C conf
Real-time checking of linear control systems using analog checksums.
IOLTS
Suvadeep Banerjee, Aritra Banerjee, Abhijit Chatterjee, Jacob A. Abraham
2013 Misc conf
Special session 12B: Panel post-silicon validation & test in huge variance era.
VTS
Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas
2012 Misc conf
A Built-In Self-Test scheme for DDR memory output timing test and measurement.
VTS
HyunJin Kim, Jacob A. Abraham
2012 J jnl
A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement.
J. Electron. Test.
HyunJin Kim, Jacob A. Abraham
2012 J jnl
A Novel fractional-n PLL Based on a Simple Reference Multiplier.
J. Circuits Syst. Comput.
Xiao Pu, Krishnaswamy Nagaraj, Jacob A. Abraham, Axel Thomsen
2012 J jnl
A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory.
Microelectron. J.
Baker Mohammad, Jacob A. Abraham
2012 Misc conf
An aging-aware flip-flop design based on accurate, run-time failure prediction.
VTS
Junyoung Park, Jacob A. Abraham
2012 Misc conf
An oscillation-based test structure for timing information extraction.
VTS
Eun Jung Jang, Anne Gattiker, Sani R. Nassif, Jacob A. Abraham
2012 J jnl
Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design.
J. Low Power Electron.
Vinod Viswanath, Jacob A. Abraham
2012 J jnl
Built-in Self Test of RF Subsystems with Integrated Detectors.
J. Electron. Test.
Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham
2012 J jnl
Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing.
J. Electron. Test.
Sachin Dileep Dasnurkar, Jacob A. Abraham
2012 A conf
FALCON: Rapid statistical fault coverage estimation for complex designs.
ITC
Shahrzad Mirkhani, Jacob A. Abraham, Toai Vo, Hong Shin Jun, Bill Eklow
2012 B conf
Functional test generation for hard to detect stuck-at faults using RTL model checking.
ETS
Mahesh Prabhu, Jacob A. Abraham
2012 J jnl
Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Byoungho Kim, Jacob A. Abraham
2012 B conf
Indirect method for random jitter measurement on SoCs using critical path characterization.
ETS
Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham
2012 J jnl
On Computing Criticality in Refactored Timing Graphs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaeyong Chung, Jacob A. Abraham
2012 A conf
On-chip source synchronous interface timing test scheme with calibration.
DATE
HyunJin Kim, Jacob A. Abraham
2012 J jnl
Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham
2012 J jnl
Phase-Aware Multitone Digital Signal Based Test for RF Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohamad A. Zeidan, Gaurab Banerjee, Ranjit Gharpurey, Jacob A. Abraham
2012 J jnl
Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaeyong Chung, Jacob A. Abraham
2012 Misc conf
Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management.
VLSI Design
Junyoung Park, H. Mert Ustun, Jacob A. Abraham
2012 C conf
Stream cipher hash based execution monitoring (SCHEM) framework for intrusion detection on embedded processors.
IOLTS
Ameya Chaudhari, Jacob A. Abraham
2012 Misc conf
Test of phase interpolators in high speed I/Os using a sliding window search.
VTS
Ji Hwan (Paul) Chun, Siew Mooi Lim, Shao Chee Ong, Jae Wook Lee, Jacob A. Abraham
2012 J jnl
Testability-Driven Statistical Path Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham
2011 A conf
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems.
ISLPED
Junyoung Park, Jacob A. Abraham
2011 J jnl
CEDA: Control-Flow Error Detection Using Assertions.
IEEE Trans. Computers
Ramtilak Vemu, Jacob A. Abraham
2011 J jnl
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Byoungho Kim, Jacob A. Abraham
2011 Misc conf
Efficient and product-representative timing model validation.
VTS
Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham
2011 J jnl
Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.
J. Electron. Test.
Kihyuk Han, Joonsung Park, Jae Wook Lee, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, Sejang Oh, Jacob A. Abraham
2011 — conf
On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test.
Asian Test Symposium
HyunJin Kim, Jacob A. Abraham
2011 — conf
Path criticality computation in parameterized statistical timing analysis.
ASP-DAC
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham
2011 — conf
Post-Silicon Timing Validation Method Using Path Delay Measurements.
Asian Test Symposium
Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham
2011 J jnl
Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model.
J. Electron. Test.
Joonsung Park, Hongjoong Shin, Jacob A. Abraham
2011 — conf
Robust power gating reactivation by dynamic wakeup sequence throttling.
ASP-DAC
Tung-Yeh Wu, Shih-Hsin Hu, Jacob A. Abraham
2011 — conf
System accuracy estimation of SRAM-based device authentication.
ASP-DAC
Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham
2011 A* conf
Testability driven statistical path selection.
DAC
Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham
2011 J jnl
Transformer-Coupled Loopback Test for Differential Mixed-Signal Dynamic Specifications.
IEEE Trans. Instrum. Meas.
Byoungho Kim, Jacob A. Abraham
2011 — conf
Tutorial: "Manufacturing test of systems-on-a-chip (SoCs)".
SoCC
Jacob A. Abraham
2010 B conf
A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control.
ETS
HyunJin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo
2010 — conf
A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces.
Asian Test Symposium
HyunJin Kim, Jacob A. Abraham
2010 — conf
A delay measurement method using a shrinking clock signal.
ACM Great Lakes Symposium on VLSI
Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham
2010 — conf
A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection.
ASP-DAC
Ji Hwan (Paul) Chun, Jae Wook Lee, Jacob A. Abraham
2010 B conf
An improved SOM-based visualization technique for DNA microarray data analysis.
IJCNN
Jagdish Chandra Patra, Jacob A. Abraham, Pramod Kumar Meher, Goutam Chakraborty
2010 — conf
At-speed Test of High-Speed DUT Using Built-Off Test Interface.
Asian Test Symposium
Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh
2010 B conf
Calibration-enabled scalable built-in current sensor compatible with very low cost ATE.
ETS
Sachin Dileep Dasnurkar, Jacob A. Abraham
2010 — conf
Estimation of maximum application-level power supply noise.
SoCC
Tung-Yeh Wu, Sriram Sambamurthy, Jacob A. Abraham
2010 — conf
High speed recursion-free CORDIC architecture.
SoCC
Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham
2010 Misc conf
Multitone digital signal based test for RF receivers.
VTS
Mohamad A. Zeidan, Aritra Banerjee, Ranjit Gharpurey, Jacob A. Abraham
2010 J jnl
On-Chip Delay Measurement Based Response Analysis for Timing Characterization.
J. Electron. Test.
Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham
2010 — conf
Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM.
ISQED
Sachin Dileep Dasnurkar, Jacob A. Abraham
2010 Misc conf
Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate.
VTS
Jaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo
2010 J jnl
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits.
J. Electron. Test.
Hongjoong Shin, Joonsung Park, Jacob A. Abraham
2010 C conf
Toward reliable SRAM-based device identification.
ICCD
Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham
2009 — conf
A Random Jitter RMS Estimation Technique for BIST Applications.
Asian Test Symposium
Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham
2009 A conf
A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA.
ICCAD
Jaeyong Chung, Jacob A. Abraham
2009 C conf
A high throughput FFT processor with no multipliers.
ICCD
Shakeel S. Abdulla, Haewoon Nam, Mark McDermot, Jacob A. Abraham
2009 C conf
An Area Efficient On-chip Static IR Drop Detector/Evaluator.
ISCAS
Tung-Yeh Wu, Samaneh Gharahi, Jacob A. Abraham
2009 — conf
Characterization of sequential cells for constraint sensitivities.
ISQED
Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal
2009 B conf
Critical Path Selection for Delay Test Considering Coupling Noise.
ETS
Rajeshwary Tayade, Jacob A. Abraham
2009 J jnl
Critical Path Selection for Delay Testing Considering Coupling Noise.
J. Electron. Test.
Rajeshwary Tayade, Jacob A. Abraham
2009 Misc conf
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL.
VLSI Design
Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham
2009 J jnl
Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level.
J. Low Power Electron.
Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham
2009 C conf
Error detection in 2-D Discrete Wavelet lifting transforms.
IOLTS
Shih-Hsin Hu, Jacob A. Abraham
2009 — conf
Functionally valid gate-level peak power estimation for processors.
ISQED
Sriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham
2009 C conf
Hybrid BiST Solution for Analog to Digital Converters with Low-cost Automatic Test Equipment Compatibility.
ISCAS
Sachin Dileep Dasnurkar, Jacob A. Abraham
2009 — conf
LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits.
Asian Test Symposium
Joonsung Park, Jaeyong Chung, Jacob A. Abraham
2009 B conf
Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.
ETS
Kihyuk Han, Joonsung Park, Jae Wook Lee, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh
2009 Misc conf
On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector.
VTS
Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham
2009 C conf
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?.
IOLTS
Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Christos A. Papachristou
2009 Misc conf
Recursive Path Selection for Delay Fault Testing.
VTS
Jaeyong Chung, Jacob A. Abraham
2009 — conf
SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000.
DFT
Shih-Hsin Hu, Tung-Yeh Wu, Jacob A. Abraham
2008 Misc conf
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.
VLSI Design
Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri
2008 A conf
A low-cost concurrent error detection technique for processor control logic.
DATE
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche
2008 — conf
A timing methodology considering within-die clock skew variations.
SoCC
Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham
2008 C conf
Adaptive SRAM memory for low power and high yield.
ICCD
Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham
2008 — conf
Analytical model for the impact of multiple input switching noise on timing.
ASP-DAC
Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham
2008 C conf
Budget-Dependent Control-Flow Error Detection.
IOLTS
Ramtilak Vemu, Jacob A. Abraham
2008 — conf
Cache Design for Low Power and High Yield.
ISQED
Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham
2008 — conf
Characterization of Standard Cells for Intra-Cell Mismatch Variations.
ISQED
Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda
2008 J jnl
Controllability of Static CMOS Circuits for Timing Characterization.
J. Electron. Test.
Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu
2008 B conf
Critical Path Selection for Delay Test Considering Coupling Noise.
ETS
Rajeshwary Tayade, Jacob A. Abraham
2008 A conf
Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems.
DATE
Neeraj Suri, Christof Fetzer, Jacob A. Abraham, Stefan Poledna, Avi Mendelson, Subhasish Mitra
2008 Misc conf
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits.
VTS
Byoungho Kim, Nash Khouzam, Jacob A. Abraham
2008 A conf
Implications of Technology Trends on System Dependability.
DATE
Jacob A. Abraham
2008 — conf
Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL.
ISVLSI
Xiao Pu, Axel Thomsen, Jacob A. Abraham
2008 B conf
Jitter Decomposition in High-Speed Communication Systems.
ETS
Qingqi Dou, Jacob A. Abraham
2008 Misc conf
Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors.
VTS
Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham
2008 Misc conf
Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems.
VTS
Qingqi Dou, Jacob A. Abraham
2008 — conf
On efficient generation of instruction sequences to test for delay defects in a processor.
ACM Great Lakes Symposium on VLSI
Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan
2008 A conf
On-chip Programmable Capture for Accurate Path Delay Test and Characterization.
ITC
Rajeshwary Tayade, Jacob A. Abraham
2008 Misc conf
Parallel Loopback Test of Mixed-Signal Circuits.
VTS
Joonsung Park, Hongjoong Shin, Jacob A. Abraham
2008 J jnl
Performance-Optimized Design for Parametric Reliability.
J. Electron. Test.
Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka
2008 J jnl
Sequential equivalence checking between system level and RTL descriptions.
Des. Autom. Embed. Syst.
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham, Jiajin Tu
2008 J jnl
Small-delay defect detection in the presence of process variations.
Microelectron. J.
Rajeshwary Tayade, Jacob A. Abraham
2007 A conf
ACCE: Automatic correction of control-flow errors.
ITC
Ramtilak Vemu, Sankar Gurumurthy, Jacob A. Abraham
2007 B conf
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors.
ETS
Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab
2007 J jnl
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems.
IEEE Trans. Computers
Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham
2007 — conf
Built-In Test of RF Mixers Using RF Amplitude Detectors.
ISQED
Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham
2007 Misc conf
Efficient Microprocessor Verification using Antecedent Conditioned Slicing.
VLSI Design
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham
2007 — conf
Estimating path delay distribution considering coupling noise.
ACM Great Lakes Symposium on VLSI
Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham
2007 J jnl
Improved verification of hardware designs through antecedent conditioned slicing.
Int. J. Softw. Tools Technol. Transf.
Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham
2007 J jnl
Predicting mixed-signal dynamic performance using optimised signature-based alternate test.
IET Comput. Digit. Tech.
Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham
2007 — conf
Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model.
ISQED
Joonsung Park, Hongjoong Shin, Jacob A. Abraham
2007 — conf
Reducing verification overhead with RTL slicing.
ACM Great Lakes Symposium on VLSI
Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham
2007 — conf
Small-Delay Defect Detection in the Presence of Process Variations.
ISQED
Rajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham
2007 Misc conf
Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications.
VTS
Byoungho Kim, Zhenhai Fu, Jacob A. Abraham
2007 Misc conf
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs.
VLSI Design
Jacob A. Abraham, Daniel G. Saab
2006 Misc conf
A Scheme for On-Chip Timing Characterization.
VTS
Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham
2006 — conf
A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters.
ATS
Hongjoong Shin, Jiseon Park, Jacob A. Abraham
2006 — conf
Adaptive Design for Performance-Optimized Robustness.
DFT
Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka
2006 C conf
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions.
MEMOCODE
Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu
2006 A conf
Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor.
ITC
Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham
2006 A conf
Automatic insertion of low power annotations in RTL for pipelined microprocessors.
DATE
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.
2006 A conf
Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble Method.
ITC
Hongjoong Shin, Joonsung Park, Jacob A. Abraham
2006 C conf
CEDA: Control-flow Error Detection through Assertions.
IOLTS
Ramtilak Vemu, Jacob A. Abraham
2006 — conf
Cache Organization for Embeded Processors: CAM-vs-SRAM.
SoCC
Baker Mohammad, Paul Bassett, Jacob A. Abraham, Adnan Aziz
2006 Misc conf
Checking Nested Properties Using Bounded Model Checking and Sequential ATPG.
VLSI Design
Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
2006 — conf
Delay Constrained Register Transfer Level Dynamic Power Estimation.
PATMOS
Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri
2006 A conf
HDL Program Slicing to Reduce Bounded Model Checking Search Overhead.
ITC
Jen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham
2006 — conf
Jitter Decomposition by Time Lag Correlation.
ISQED
Qingqi Dou, Jacob A. Abraham
2006 — conf
Jitter decomposition in ring oscillators.
ASP-DAC
Qingqi Dou, Jacob A. Abraham
2006 B conf
Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters.
ETS
Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham
2006 Misc conf
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits.
VTS
Hongjoong Shin, Byoungho Kim, Jacob A. Abraham
2006 — conf
Taming the Complexity of STE-based Design Verification Using Program Slicing.
HLDVT
Vivekananda M. Ve. Andersen, Jacob A. Abraham
2005 J jnl
A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor.
Formal Methods Syst. Des.
Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham
2005 B conf
An Emulation Model for Sequential ATPG-Based Bounded Model Checking.
FPL
Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
2005 A conf
Automated mapping of pre-computed module-level test sequences to processor instructions.
ITC
S. Guramurthy, Shobha Vasudevan, Jacob A. Abraham
2005 C conf
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core.
ICCD
Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham
2005 A conf
Testing and debugging delay faults in dynamic circuits.
ITC
Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham
2004 — conf
A low latency and low power dynamic Carry Save Adder.
ISCAS (2)
Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka
2004 — conf
An efficient linearity test for on-chip high speed ADC and DAC using loop-back.
ACM Great Lakes Symposium on VLSI
Ji Hwan (Paul) Chun, Hak-Soo Yu, Jacob A. Abraham
2004 B conf
Delay fault testing and silicon debug using scan chains.
ETS
Ramyanshu Datta, Antony Sebastine, Jacob A. Abraham
2004 — conf
Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter.
ASP-DAC
Jianhua Gan, Shouli Yan, Jacob A. Abraham
2004 — conf
Efficient Model Checking of Hardware Using Conditioned Slicing.
AVoCS
Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham
2004 A conf
Formal Verification of a System-on-Chip Using Computation Slicing.
ITC
Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra
2004 — conf
LFSR-based BIST for analog circuits using slope detection.
ACM Great Lakes Symposium on VLSI
Hongjoong Shin, Hak-Soo Yu, Jacob A. Abraham
2004 A conf
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
ITC
Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham
2004 — conf
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
MTV
Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham
2004 — conf
On-chip delay measurement for silicon debug.
ACM Great Lakes Symposium on VLSI
Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham
2004 A conf
Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation.
ITC
Hak-Soo Yu, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham
2004 Misc conf
Prediction of Analog Performance Parameters Using Oscillation Based Test.
VTS
Ashwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee
2004 Misc conf
Program Slicing for ATPG-Based Property Checking.
VLSI Design
Vivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham
2004 A conf
Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters.
ITC
Ashwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee
2004 — conf
Static program transformations for efficient software model checking.
IFIP Congress Topical Sessions
Shobha Vasudevan, Jacob A. Abraham
2004 J jnl
Subband filtering for time and frequency analysis of mixed-signal circuit testing.
IEEE Trans. Instrum. Meas.
Jeongjin Roh, Jacob A. Abraham
2004 Misc conf
Towards The Complete Elimination of Gate/Switch Level Simulations.
VLSI Design
Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
2004 A conf
Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.
ITC
Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu
2003 J jnl
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
J. Electron. Test.
Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri
2003 J jnl
A comprehensive signature analysis scheme for oscillation-test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jeongjin Roh, Jacob A. Abraham
2003 Misc conf
DSP-Based Statistical Self Test of On-Chip Converters.
VTS
Hak-Soo Yu, Sungbae Hwang, Jacob A. Abraham
2003 — conf
Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array.
ACM Great Lakes Symposium on VLSI
Jianhua Gan, Shouli Yan, Jacob A. Abraham
2003 Misc conf
Effects of Multi-cycle Sensitization on Delay Tests.
VLSI Design
Arun Krishnamachary, Jacob A. Abraham
2003 — conf
Efficient loop-back testing of on-chip ADCs and DACs.
ASP-DAC
Hak-Soo Yu, Jacob A. Abraham, Sungbae Hwang, Jeongjin Roh
2003 Misc conf
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.
VLSI Design
Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula
2003 Misc conf
Model Checking of Security Protocols with Pre-configuration.
WISA
Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra
2003 C conf
On-Line Error Detecting Constant Delay Adder.
IOLTS
Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala
2003 — conf
Quadruple Time Redundancy Adders.
DFT
Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.
2003 J jnl
Test data compression and test time reduction using an embedded microprocessor.
IEEE Trans. Very Large Scale Integr. Syst.
Sungbae Hwang, Jacob A. Abraham
2002 — conf
A Comprehensive Fault Model for Deep Submicron Digital Circuits.
DELTA
Jacob A. Abraham, Arun Krishnamachary, Raghuram S. Tupuri
2002 — conf
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation.
ASP-DAC/VLSI Design
Hak-Soo Yu, Jacob A. Abraham
2002 J jnl
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table.
Formal Methods Syst. Des.
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
2002 A conf
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis.
DATE
Vivekananda M. Vedula, Jacob A. Abraham
2002 A* conf
False timing path identification using ATPG techniques and delay-based information.
DAC
Jing Zeng, Magdy S. Abadir, Jacob A. Abraham
2002 Misc conf
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?
VTS
Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
2002 B conf
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm.
FPL
Daniel G. Saab, Fatih Kocan, Jacob A. Abraham
2002 — conf
Native Mode Functional Self-Test Generation for Systems-on-Chip.
ISQED
Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham
2002 A conf
Optimal BIST Using an Embedded Microprocessor.
ITC
Sungbae Hwang, Jacob A. Abraham
2002 Misc conf
Program Slicing for Hierarchical Test Generation.
VTS
Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra
2002 A* conf
Property Checking via Structural Analysis.
CAV
Jason Baumgartner, Andreas Kuehlmann, Jacob A. Abraham
2002 — conf
Selective-run built-in self-test using an embedded processor.
ACM Great Lakes Symposium on VLSI
Sungbae Hwang, Jacob A. Abraham
2002 — conf
Test generation for resistive opens in CMOS.
ACM Great Lakes Symposium on VLSI
Arun Krishnamachary, Jacob A. Abraham
2002 A conf
Verifying Properties Using Sequential ATPG.
ITC
Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab
2001 — conf
A language formalism for verification of PowerPC
HLDVT
Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
2001 Misc conf
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them?
VTS
Henry Chang, Steve Dollens, Gordon W. Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham
2001 — conf
Communication Space Reduction for Formal Verification of Secure Authentication Protocols.
WECWIS
Kyoil Kim, Jacob A. Abraham
2001 J jnl
Design and Development Paradigm for Industrial Formal Verification CAD Tools.
IEEE Des. Test Comput.
Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham
2001 J jnl
Frequency Response Verification of Analog Circuits Using Global Optimization Techniques.
J. Electron. Test.
Suresh Seshadri, Jacob A. Abraham
2001 A conf
Full chip false timing path identification: applications to the PowerPCTM microprocessors.
DATE
Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
2001 Misc conf
Timing Verification and Delay Test Generation for Hierarchical Designs.
VLSI Design
Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri
2001 — conf
Using Abstract Specifications to Verify PowerPC
CHARME
Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
2000 Misc conf
A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test.
VTS
Jeongjin Roh, Jacob A. Abraham
2000 Misc conf
A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters.
VLSI Design
Jeongjin Roh, Jacob A. Abraham
2000 — conf
A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor.
LATW
Jayanta Batra, Magdy S. Abadir, Jacob A. Abraham
2000 — conf
A novel methodology for hierarchical test generation using functional constraint composition.
HLDVT
Vivekananda M. Vedula, Jacob A. Abraham
2000 — conf
A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC
CICC
Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
2000 C conf
An Adder Using Charge Sharing and its Application in DRAMs.
ICCD
Hak-Soo Yu, Songjun Lee, Jacob A. Abraham
2000 J jnl
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation.
J. Electron. Test.
Jian Shen, Jacob A. Abraham
2000 Misc conf
Automatic Validation Test Generation Using Extracted Control Models.
VLSI Design
Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham
2000 — conf
Causality based generation of directed test cases.
ASP-DAC
Nina Saxena, Jacob A. Abraham, Avijit Saha
2000 Misc conf
Hierarchical Test Generation for Systems On a Chip.
VLSI Design
Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab
2000 — conf
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA.
CICC
Tarachand Pagarani, Fatih Kocan, Daniel G. Saab, Jacob A. Abraham
2000 Misc conf
Performance and Functional Verification of Microprocessors.
VLSI Design
Pradip Bose, Jacob A. Abraham
2000 J jnl
Validating PowerPC Microprocessor Custom Memories.
IEEE Des. Test Comput.
Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
2000 Misc conf
Validation of PowerPC(tm) Custom Memories using Symbolic Simulation.
VTS
Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
2000 A conf
Verification of Delta-Sigma Converters Using Adaptive Regression Modeling.
ICCAD
Jeongjin Roh, Suresh Seshadri, Jacob A. Abraham
1999 A conf
An Efficient Filter-Based Approach for Combinational Verification.
DATE
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1999 J jnl
An efficient filter-based approach for combinational verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1999 A conf
Critical path identification and delay tests of dynamic circuits.
ITC
Kyung Tek Lee, Jacob A. Abraham
1999 J jnl
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection.
IEEE Trans. Parallel Distributed Syst.
Zeyad Alkhalifa, V. S. S. Nair, Narayanan Krishnamurthy, Jacob A. Abraham
1999 A* conf
Detecting False Timing Paths: Experiments on PowerPC Microprocessors.
DAC
Richard Raimi, Jacob A. Abraham
1999 — conf
Formal Checking of Properties in Complex Systems Using Abstractions.
Great Lakes Symposium on VLSI
Dinos Moundanos, Jacob A. Abraham
1999 A* conf
Functional Verification of the Equator MAP1000 Microprocessor.
DAC
Jian Shen, Jacob A. Abraham, Dave Baker, Tony Hurson, Martin Kinkade, Gregorio Gervasio, Chen-Chau Chu, Guanghui Hu
1999 Misc conf
FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model.
VLSI Design
Rathish Jayabharathi, Manuel A. d'Abreu, Jacob A. Abraham
1999 C conf
Improving Witness Search Using Orders on States.
ICCD
Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham
1999 J jnl
On Design Validation Using Verification Technology.
J. Electron. Test.
Dinos Moundanos, Jacob A. Abraham
1999 A conf
Position Statement: Increasing Test Coverage in a VLSI Design Course.
ITC
Jacob A. Abraham
1999 A conf
Subband filtering scheme for analog and mixed-signal circuit testing.
ITC
Jeongjin Roh, Jacob A. Abraham
1999 A* conf
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor.
DAC
Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham
1999 — conf
Transistor Level Synthesis for Static CMOS Combinational Circuits.
Great Lakes Symposium on VLSI
Chia-Pin R. Liu, Jacob A. Abraham
1999 Misc conf
Verification of Processor Microarchitectures.
VTS
Jian Shen, Jacob A. Abraham
1998 J jnl
Abstraction Techniques for Validation Coverage Analysis and Test Generation.
IEEE Trans. Computers
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote
1998 Misc conf
Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits.
VTS
Kyung Tek Lee, Clay Nordquist, Jacob A. Abraham
1998 — conf
From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel).
FTCS
Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell
1998 A conf
High-level design validation and test.
ICCAD
Sujit Dey, Jacob A. Abraham, Yervant Zorian
1998 A conf
Lightweight guided random simulation.
ISSRE
Robert W. Sumners, Parminder Chhabra, Jacob A. Abraham
1998 J jnl
Memory Distribution: Techniques and Practice for CAD Applications.
Parallel Comput.
Craig M. Chase, Prakash Arunachalam, Jacob A. Abraham
1998 A conf
Native mode functional test generation for processors with applications to self test and design validation.
ITC
Jian Shen, Jacob A. Abraham
1998 J jnl
Signature analysis for analog and mixed-signal circuit test response compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham
1998 J jnl
Synthesis of Native Mode Self-Test Programs.
J. Electron. Test.
Jian Shen, Jacob A. Abraham
1998 C conf
To model check or not to model check.
ICCD
Nina Saxena, Jason Baumgartner, Avijit Saha, Jacob A. Abraham
1998 Misc conf
Using Verification Technology for Validation Coverage Analysis and Test Generation.
VTS
Dinos Moundanos, Jacob A. Abraham
1997 A conf
A Novel Functional Test Generation Method for Processors Using Commercial ATPG.
ITC
Raghuram S. Tupuri, Jacob A. Abraham
1997 Misc conf
A Novel Hierarchical Test Generation Method for Processors.
VLSI Design
Raghuram S. Tupuri, Jacob A. Abraham
1997 Misc conf
A Novel Solution for Chip-Level Functional Timing Verification.
VTS
Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham
1997 J jnl
An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems.
J. Electron. Test.
Hoon Chang, Jacob A. Abraham
1997 J jnl
Automatic verification of implementations of large circuits against HDL specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos
1997 — conf
Hierarchical Specification of System Behavior.
HASE
Robert W. Sumners, Jacob A. Abraham
1997 J jnl
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions.
IEEE Trans. Computers
Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
1997 Misc conf
Microprocessor Test and Validation: Any New Avenues?
VTS
Magdy S. Abadir, Jacob A. Abraham, Hong Hao, C. Hunter, Wayne M. Needham, Ron G. Walther
1997 A* conf
On Combining Formal and Informal Verification.
CAV
Jun Yuan, Jian Shen, Jacob A. Abraham, Adnan Aziz
1997 Misc conf
T4: Verification.
VLSI Design
Rajesh Raina, Jacob A. Abraham, A. K. Pujari
1996 — conf
A Hierarchal Approach for Power Reduction in VLSI Chips.
Great Lakes Symposium on VLSI
Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu
1996 A conf
A Unified Framework for Design Validation and Manufacturing Test.
ITC
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote
1996 Misc conf
A novel test generation approach for parametric faults in linear analog circuits .
VTS
Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham
1996 J jnl
A unified approach for fault simulation of linear mixed-signal circuits.
J. Electron. Test.
Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
1996 J jnl
Analog Testing with Time Response Parameters.
IEEE Des. Test Comput.
Ashok Balivada, Jin Chen, Jacob A. Abraham
1996 J jnl
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Daniel G. Saab, Youssef Saab, Jacob A. Abraham
1996 A conf
Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor.
ITC
Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham
1996 J jnl
Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes.
IEEE Trans. Computers
V. S. S. Nair, Jacob A. Abraham, Prithviraj Banerjee
1996 Misc conf
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.
VTS
Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham
1996 Misc conf
On More Efficient Combinational ATPG Using Functional Learning.
VLSI Design
Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1996 Misc conf
Practical Test and DFT for Next Generation VLSI.
VLSI Design
Jacob A. Abraham, Gopi Ganapathy
1995 — conf
A memory distribution mechanism for object oriented applications.
SPDP
Prakash Arunachalam, Craig M. Chase, Jacob A. Abraham
1995 — conf
Automated verification of temporal properties specified as state machines in VHDL.
Great Lakes Symposium on VLSI
Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell
1995 C conf
Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors.
ICCD
Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham
1995 Misc conf
Efficient multisine testing of analog circuits.
VLSI Design
Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
1995 Misc conf
Efficient variable ordering and partial representation algorithm.
VLSI Design
Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross
1995 J jnl
FERRARI: A Flexible Software-Based Fault and Error Injection System.
IEEE Trans. Computers
Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham
1995 Misc conf
Verification of transient response of linear analog circuits.
VTS
Ashok Balivada, Yatin Vasant Hoskote, Jacob A. Abraham
1994 C conf
A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic.
ICCD
Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham
1994 C conf
A Signature Analyzer for Analog and Mixed-signal Circuits.
ICCD
Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
1994 — conf
A new scheme to compute variable orders for binary decision diagrams.
Great Lakes Symposium on VLSI
Jawahar Jain, James R. Bitner, Dinos Moundanos, Jacob A. Abraham, Donald S. Fussell
1994 — conf
Abstraction of data path registers for multilevel verification of large circuits.
Great Lakes Symposium on VLSI
Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell
1994 J jnl
An efficient critical path tracing algorithm for sequential circuits.
Microprocess. Microprogramming
Hoon Chang, Jacob A. Abraham
1994 C conf
Architectural Performance Verification: PowerPC
ICCD
S. Surya, Pradip Bose, Jacob A. Abraham
1994 J jnl
BiCMOS logic testing.
IEEE Trans. Very Large Scale Integr. Syst.
Marc E. Levitt, Kaushik Roy, Jacob A. Abraham
1994 — conf
Efficient Algorithmic Circuit Verification Using Indexed BDDs.
FTCS
James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
1994 Misc conf
Impact of behavioral modifications for testability.
VTS
Thomas Thomas, Praveen Vishakantaiah, Jacob A. Abraham
1994 A conf
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0.
ICCAD
Daniel G. Saab, Youssef Saab, Jacob A. Abraham
1994 A* conf
Microprocessor Testing: Which Technique is Best? (Panel).
DAC
Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
1994 A conf
RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults.
ICCAD
Abhijit Chatterjee, Jacob A. Abraham
1994 Misc conf
Verification of Circuits Described in VHDL through Extraction of Design Intent.
VLSI Design
Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell
1993 J jnl
A Framework for Distributed VLSI Simulation on a Network of Workstations.
Simul.
Sankaran Karthik, Jacob A. Abraham
1993 C conf
AMBIANT: Automatic Generation of Behavioral Modifications for Testability.
ICCD
Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir
1993 A conf
Adding capability checks enhances error detection and isolation in object-based systems.
ISSRE
Nasser A. Kanawati, Ghani A. Kanawati, Jacob A. Abraham
1993 J jnl
Benchmarking Parallel Processing Platforms: An Applications Perspective.
IEEE Trans. Parallel Distributed Syst.
Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
1993 A conf
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET.
ITC
Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab
1993 J jnl
Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits.
Simul.
Robert B. Mueller-Thuns, Joseph T. Rahmeh, Jacob A. Abraham, Jalal A. Wehbeh, Daniel G. Saab
1993 A* conf
DRAFTS: Discretized Analog Circuit Fault Simulator.
DAC
Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
1993 J jnl
Fault simulation of linear analog circuits.
J. Electron. Test.
Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
1993 A conf
Fault-based automatic test generator for linear analog circuits.
ICCAD
Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
1993 Misc conf
Generation of testable designs from behavioral descriptions using high level synthesis tools.
VTS
Kamal K. Varma, Praveen Vishakantaiah, Jacob A. Abraham
1993 — conf
Impact of Behavioral Learning on the Compilation of Sequential Circuit Tests.
FTCS
Praveen Vishakantaiah, Jacob A. Abraham
1993 C conf
MIXER: Mixed-Signal Fault Simulator.
ICCD
Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
1993 Misc conf
Optimizations for Behavioral/RTL Simulation.
VLSI Design
Sankaran Karthik, Jacob A. Abraham, Raymond P. Voith
1993 A* conf
Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor.
DAC
Gopi Ganapathy, Jacob A. Abraham
1993 A* conf
VIPER: An Efficient Vigorously Sensitizable Path Extractor.
DAC
Hoon Chang, Jacob A. Abraham
1993 J jnl
VLSI logic and fault simulation on general-purpose parallel computers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
1992 A* conf
Automatic Test Knowledge Extraction from VHDL (ATKET).
DAC
Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir
1992 A conf
Automatic test generation for linear digital systems with bi-level search using matrix transform methods.
ICCAD
Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu
1992 A conf
CRIS: a test cultivation program for sequential VLSI circuits.
ICCAD
Daniel G. Saab, Youssef Saab, Jacob A. Abraham
1992 — conf
Compiler-Assisted Static Checkpoint Insertion.
FTCS
Junsheng Long, W. Kent Fuchs, Jacob A. Abraham
1992 C conf
Distributed VLSI Simulation on a Network of Workstations.
ICCD
Sankaran Karthik, Jacob A. Abraham
1992 — conf
FERRARI: A Tool for The Validation of System Dependability Properties.
FTCS
Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham
1992 J jnl
Generation and evaluation of current and logic tests for switch-level sequential circuits.
J. Electron. Test.
Chun-Hung Chen, Jacob A. Abraham
1992 Misc conf
Hierarchical fault modeling for analog and mixed-signal circuits.
VTS
Naveena Nagi, Jacob A. Abraham
1992 J jnl
Probabilistic Evaluation of On-Line Checks in Fault-Tolerant Multiprocessor Systems.
IEEE Trans. Computers
V. S. S. Nair, Yatin Vasant Hoskote, Jacob A. Abraham
1992 J jnl
Probabilistic Verification of Boolean Functions.
Formal Methods Syst. Des.
Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell
1992 A conf
Sequential Redundancy Identification Using Verification Techniques.
ITC
John Moondanos, Jacob A. Abraham
1992 J jnl
Test compaction for sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham
1991 — conf
Design and evaluation of fault tolerance techniques for highly parallel architectures.
Great Lakes Symposium on VLSI
Jacob A. Abraham
1991 J jnl
Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors.
Digit. Signal Process.
Abhijit Chatterjee, Rabindra K. Roy, Jacob A. Abraham, Janak H. Patel
1991 — conf
Functional abstraction of logic gates for switch-level simulation.
EURO-DAC
David T. Blaauw, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham
1991 A conf
Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality.
ITC
Gopi Ganapathy, Jacob A. Abraham
1991 A conf
High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms.
ITC
Chun-Hung Chen, Jacob A. Abraham
1991 C conf
Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter.
ICCD
Sankaran Karthik, Indira de Souza, Joseph T. Rahmeh, Jacob A. Abraham
1991 — conf
Parallel switch-level simulation for VLSI.
EURO-DAC
Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham
1991 A conf
Probabilistic Design Verification.
ICCAD
Jawahar Jain, James R. Bitner, Donald S. Fussell, Jacob A. Abraham
1991 J jnl
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model.
IEEE Trans. Computers
Abhijit Chatterjee, Jacob A. Abraham
1991 J jnl
Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling.
J. Electron. Test.
Abhijit Chatterjee, Jacob A. Abraham
1991 J jnl
The use of RTL descriptions in accurate timing verification and test generation (VLSI).
IEEE J. Solid State Circuits
Kaushik Roy, Jacob A. Abraham
1990 J jnl
A reconfigurable parallel signature analyzer for concurrent error correction in DRAM.
IEEE J. Solid State Circuits
Pinaki Mazumder, Janak H. Patel, Jacob A. Abraham
1990 A conf
A study of faulty signatures using a matrix formulation.
ITC
John C. Chan, Jacob A. Abraham
1990 J jnl
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor.
IEEE Trans. Computers
Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham
1990 C conf
Automatic classification of node types in switch-level descriptions.
ICCD
David T. Blaauw, Prithviraj Banerjee, Jacob A. Abraham
1990 C conf
BiCMOS fault models: is stuck-at adequate?
ICCD
Marc E. Levitt, Kaushik Roy, Jacob A. Abraham
1990 — conf
Derivation of signal flow for switch-level simulation.
EURO-DAC
David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham
1990 A conf
Design of a scalable parallel switch-level simulator for VLSI.
SC
Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham
1990 C conf
Fault grading of large digital systems.
ICCD
Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham
1990 — conf
Forward Recovery Using Checkpointing in Parallel Systems.
ICPP (1)
Junsheng Long, W. Kent Fuchs, Jacob A. Abraham
1990 — conf
Hierarchical design and analysis of fault-tolerant multiprocessor systems using concurrent error detection.
FTCS
Suku Nair, Jacob A. Abraham
1990 J jnl
Hierarchical multi-level fault simulation of large systems.
J. Electron. Test.
Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham
1990 — conf
High level test generation using data flow descriptions.
EURO-DAC
Kaushik Roy, Jacob A. Abraham
1990 A conf
Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm.
ICCAD
Chun-Hung Chen, Jacob A. Abraham
1990 J jnl
Physical design of testable VLSI: techniques and experiments.
IEEE J. Solid State Circuits
Marc E. Levitt, Jacob A. Abraham
1990 J jnl
Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays.
IEEE Trans. Computers
V. S. S. Nair, Jacob A. Abraham
1990 A conf
SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction.
ICCAD
David T. Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham
1990 A* conf
Speed Up of Test Generation Using High-Level Primitives.
DAC
Ramachandra P. Kunda, Jacob A. Abraham, Bharat Deep Rathi, Prakash Narain
1990 J jnl
The Testability of Generalized Counters Under Multiple Faulty Cells.
IEEE Trans. Computers
Abhijit Chatterjee, Jacob A. Abraham
1989 A* conf
A Novel Approach to Accurate Timing Verification Using RTL Descriptions.
DAC
Kaushik Roy, Jacob A. Abraham
1989 — conf
Advances in VLSI-Testing.
IFIP Congress
Jacob A. Abraham
1989 A conf
An Easily Computed Functional Level Testability Measure.
ITC
Kurt H. Thearling, Jacob A. Abraham
1989 A* conf
Automatic Generation of Behavioral Models from Switch-Level Descriptions.
DAC
David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh
1989 A* conf
Average Interconnection Length and Interconnection Distribution Based on Rent's Rule.
DAC
Carol V. Gura, Jacob A. Abraham
1989 A conf
Portable parallel logic and fault simulation.
ICCAD
Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
1989 A conf
Synthesis of delay fault testable combinational logic.
ICCAD
Kaushik Roy, Jacob A. Abraham, Kaushik De, Stephen L. Lusky
1989 A conf
The Economics of Scan Design.
ITC
Marc E. Levitt, Jacob A. Abraham
1988 — conf
An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor.
FTCS
Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Jacob A. Abraham
1988 A conf
CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits.
ICCAD
Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Jacob A. Abraham, Joseph T. Rahmeh
1988 A conf
Compaction of ATPG-generated test sequences for sequential circuits.
ICCAD
Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh
1988 A conf
DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests.
ITC
M. J. Marlett, Jacob A. Abraham
1988 A* conf
Fault Simulation in a Distributed Environment.
DAC
Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers
1988 — conf
Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing.
ICPP (1)
Jing-Yang Jou, Jacob A. Abraham
1988 J jnl
Fault-Tolerant FFT Networks.
IEEE Trans. Computers
Jing-Yang Jou, Jacob A. Abraham
1988 — conf
General linear codes for fault-tolerant matrix operations on processor arrays.
FTCS
Suku Nair, Jacob A. Abraham
1988 A* conf
Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics.
DAC
Carol V. Gura, Jacob A. Abraham
1988 A conf
NCUBE: an automatic test generation program for iterative logic arrays.
ICCAD
Abhijit Chatterjee, Jacob A. Abraham
1987 J jnl
Comparison and Diagnosis of Large Replicated Files.
IEEE Trans. Software Eng.
W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham
1987 J jnl
Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
William A. Rogers, John F. Guzolek, Jacob A. Abraham
1987 J jnl
Fault Tolerance Techniques for Systolic Arrays.
Computer
Jacob A. Abraham, Prithviraj Banerjee, Chien-Yi Chen, W. Kent Fuchs, Sy-Yen Kuo, A. L. Narasimha Reddy
1987 J jnl
On the C-Testability of Generalized Counters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abhijit Chatterjee, Jacob A. Abraham
1986 A conf
A Probabilistic Model of Algorithm-Based Fault Tolerance in Array Processors for Real-Time Systems.
RTSS
Prithviraj Banerjee, Jacob A. Abraham
1986 A conf
Approaches to Circuit Level Design for Testability.
ITC
Robert H. Fujii, Jacob A. Abraham
1986 J jnl
Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems.
IEEE Trans. Computers
Prithviraj Banerjee, Jacob A. Abraham
1986 — conf
Design of Systems with Concurrent Error Detection Using Software Redundancy.
FJCC
Kien A. Hua, Jacob A. Abraham
1986 J jnl
Distributed Control of Computer Systems.
IEEE Trans. Computers
Timothy C. K. Chou, Jacob A. Abraham
1986 J jnl
FAUST: An MOS Fault Simulator with Timing Information.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham
1986 J jnl
Fault and error models for VLSI.
Proc. IEEE
Jacob A. Abraham, W. Kent Fuchs
1986 J jnl
Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures.
Proc. IEEE
Jing-Yang Jou, Jacob A. Abraham
1986 — conf
Low-Cost Comparison and Diagnosis of Large Remotely Located Files.
Symposium on Reliability in Distributed Software and Database Systems
W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham
1986 — conf
On the Design of Fault-Tolerant Systolic Arrays with Linear Cells.
FJCC
Chien-Yi Chen, Jacob A. Abraham
1986 — conf
Research in Reliable VLSI Architectures at the University of Illinois.
FJCC
Jacob A. Abraham
1986 A conf
Structured Functional Level Test Generation Using Binary Decision Diagrams.
ITC
Hongtao P. Chang, William A. Rogers, Jacob A. Abraham
1986 A* conf
Transistor-level test generation for physical failures in CMOS circuits.
DAC
Hsi-Ching Shih, Jacob A. Abraham
1985 J jnl
A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Prithviraj Banerjee, Jacob A. Abraham
1985 A conf
CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator.
ITC
William A. Rogers, Jacob A. Abraham
1985 J jnl
Design of Testable CMOS Logic Circuits Under Arbitrary Delays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Niraj K. Jha, Jacob A. Abraham
1985 — conf
High level hierarchical fault simulation techniques.
ACM Conference on Computer Science
William A. Rogers, Jacob A. Abraham
1985 A conf
Self-Test for Microprocessors.
ITC
Robert H. Fujii, Jacob A. Abraham
1985 A* conf
TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology.
ISCA
Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham
1984 J jnl
Algorithm-Based Fault Tolerance for Matrix Operations.
IEEE Trans. Computers
Kuang-Hua Huang, Jacob A. Abraham
1984 J jnl
Characterization and Testing of Physical Failures in MOS Logic Circuits.
IEEE Des. Test
Prithviraj Banerjee, Jacob A. Abraham
1984 A conf
Design of Test Pattern Generators for Built-In Test.
ITC
Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham
1984 A* conf
Fault-Secure Algorithms for Multiple-Processor Systems.
ISCA
Prithviraj Banerjee, Jacob A. Abraham
1984 J jnl
Functional Testing of Microprocessors.
IEEE Trans. Computers
Dhananjay Brahme, Jacob A. Abraham
1983 A* conf
Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets
ISCA
Richard L. Norton, Jacob A. Abraham
1983 A* conf
Concurrent Error Detection in VLSI Interconnection Networks
ISCA
W. Kent Fuchs, Jacob A. Abraham, Kuang-Hua Huang
1983 A conf
Generating Tests for Physical Failures in MOS Logic Circuits.
ITC
Prithviraj Banerjee, Jacob A. Abraham
1983 A conf
Incorporating Test Technology into an Undergraduate Curriculum.
ITC
Jacob A. Abraham
1983 J jnl
Load Redistribution Under Failure in Distributed Systems.
IEEE Trans. Computers
Timothy C. K. Chou, Jacob A. Abraham
1982 B conf
Efficient parallel algorithms for processor arrays.
ICPP
Kuang-Hua Huang, Jacob A. Abraham
1982 J jnl
Load Balancing in Distributed Systems.
IEEE Trans. Software Eng.
Timothy C. K. Chou, Jacob A. Abraham
1982 A* conf
Test generation for programmable logic arrays.
DAC
Pradip Bose, Jacob A. Abraham
1982 B conf
Using write back cache to improve performance of multi-user multiprocessors.
ICPP
Richard L. Norton, Jacob A. Abraham
1981 J jnl
Design of Testable Structures Defined by Simple Loops.
IEEE Trans. Computers
Jacob A. Abraham, Daniel Gajski
1981 A conf
Functional Level Test Generation for Complex Digital Systems.
ITC
Jacob A. Abraham
1980 J jnl
Test Generation for Microprocessors.
IEEE Trans. Computers
Satish M. Thatte, Jacob A. Abraham
1978 J jnl
Efficient Algorithms for Testing Semiconductor Random-Access Memories.
IEEE Trans. Computers
Ravindra Nair, Satish M. Thatte, Jacob A. Abraham
1975 J jnl
A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks.
IEEE Trans. Computers
Jacob A. Abraham
1974 J jnl
An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks.
IEEE Trans. Computers
Jacob A. Abraham, Daniel P. Siewiorek