Jack S. N. Jean

25 papers B 1Misc 6Journal 10Unranked 8
YearRankTypeTitle / Venue / Authors
2012 J jnl
Architecture and operating system support for two-dimensional runtime partial reconfiguration.
J. Supercomput.
Fei Wang, Jack S. N. Jean
2010 — conf
Parameterized AND-OR Trees for FPGA Design Space Exploration.
ERSA
Srikanth Nadella, Andrew Dittes, Jack S. N. Jean
2006 — conf
Architectural Support for Runtime 2D Partial Reconfiguration.
ERSA
Fei Wang, Jack S. N. Jean
2005 — conf
Aspect Ratio Effects on Reconfigurable Computing.
ERSA
Fei Wang, Jack S. N. Jean, Shuxia Sun
2004 — conf
Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers.
ERSA
Xinzhong Guo, Jack S. N. Jean
2003 — conf
A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers.
Engineering of Reconfigurable Systems and Algorithms
Jack S. N. Jean, Xinzhong Guo, Fei Wang, Lei Song, Ying Zhang
2003 J jnl
Mapping of generalized template matching onto reconfigurable computers.
IEEE Trans. Very Large Scale Integr. Syst.
Xuejun Liang, Jack S. N. Jean
2001 J jnl
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems.
J. Supercomput.
Xuejun Liang, Jack S. N. Jean, Karen A. Tomko
2000 J jnl
Automatic Target Recognition with Dynamic Reconfiguration.
J. VLSI Signal Process.
Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko, Yan Wang
2000 Misc conf
Interface Design for the Mapping of Generalized Template Matching on Reconfigurable Systems.
PDPTA
Xuejun Liang, Jack S. N. Jean
1999 Misc conf
Accelerating an IR Automatic Target Recognition Application with FPGAs.
FCCM
Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko
1999 J jnl
Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation.
VLSI Design
Hong K. Kim, Jack S. N. Jean
1999 Misc conf
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems.
PDPTA
Jack S. N. Jean, Xuejun Liang, Karen A. Tomko
1999 J jnl
Dynamic Reconfiguration to Support Concurrent Applications.
IEEE Trans. Computers
Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook
1999 J jnl
Processor array design with FPGA area constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Joseph A. Fernando, Jack S. N. Jean
1998 Misc conf
Dynamic Reconfiguration to Support Concurrent Applications.
FCCM
Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Robert Cook, Jignesh Shah
1998 B conf
Parallel Optimistic Logic Simulation with Event Lookahead.
ICPP
Hong K. Kim, Jack S. N. Jean
1996 — conf
Concurrency Preserving Rartitioning (CPP) for Parallel Logic Simulation.
Workshop on Parallel and Distributed Simulation
Hong K. Kim, Jack S. N. Jean
1995 — conf
Interfacing FPGA/VLSI Processor Arrays.
ASAP
Joseph A. Fernando, Jack S. N. Jean
1994 J jnl
Segmentation of merged characters by neural networks and shortest path.
Pattern Recognit.
Jin Wang, Jack S. N. Jean
1994 J jnl
Weight smoothing to improve network generalization.
IEEE Trans. Neural Networks
Jack S. N. Jean, Jin Wang
1993 J jnl
Resolving multifont character confusion with neural networks.
Pattern Recognit.
Jin Wang, Jack S. N. Jean
1993 Misc conf
Segmentation of Merged Characters by Neural Networks and Shortest-Path.
SAC
Jin Wang, Jack S. N. Jean
1990 Misc conf
A new distance measure for binary images.
ICASSP
Jack S. N. Jean
1990 — conf
Fault-tolerant array processors using N-and-half-track switches.
ASAP
Jack S. N. Jean